)]}'
{"specs/stein/approved/cyborg-nova-placement.rst":[{"author":{"_account_id":28766,"name":"Brian Xu","email":"brianx@xilinx.com"},"change_message_id":"c6abbfe97269d3db579760ff777f5d012062841e","unresolved":false,"context_lines":[{"line_number":189,"context_line":"The following list of Cyborg properties is not comprehensive. Their usage is"},{"line_number":190,"context_line":"illustrated in the section `Usage in device profiles`_."},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"* ``bitstream_id:\u003cid\u003e``: Specifies the Glance image id of a bitstream."},{"line_number":193,"context_line":""},{"line_number":194,"context_line":"* ``bitstream_at_runtime``: Specifies the need to initiate FPGA programming"},{"line_number":195,"context_line":"  at runtime (see `Use cases`_)."}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_82b714d8","line":192,"updated":"2018-09-26 22:05:25.000000000","message":"Can the glance image be seen by all tenants? For AFaaS, the bitstreams are provided by the cloud vendor, so it makes sense to save the bitstream in glance. But for DaaS, the bitstreams are owned by tenants, so a tenant doesn\u0027t want to others see there bitstreams. Imagine a case in DaaS, after the user developed a bitstream and saved it to the private object store, and then he/she wants to launch an instance with request-time programming, how this can be done?","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"0137b7336b8844bd1557f769eaa4d0c98f0fe16b","unresolved":false,"context_lines":[{"line_number":189,"context_line":"The following list of Cyborg properties is not comprehensive. Their usage is"},{"line_number":190,"context_line":"illustrated in the section `Usage in device profiles`_."},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"* ``bitstream_id:\u003cid\u003e``: Specifies the Glance image id of a bitstream."},{"line_number":193,"context_line":""},{"line_number":194,"context_line":"* ``bitstream_at_runtime``: Specifies the need to initiate FPGA programming"},{"line_number":195,"context_line":"  at runtime (see `Use cases`_)."}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_e1363fb4","line":192,"in_reply_to":"3f79a3b5_82b714d8","updated":"2018-10-05 17:09:21.000000000","message":"Access to Glance images can be limited, and have 4 levels:\n$ openstack image create ... [--public | --private | --community | --shared] ...\nPrivate is default. Specific tenants can be given access via:\n$ openstack image add project \u003cimage\u003e \u003cproject\u003e\n\nCyborg should retrieve bitstream images with the user\u0027s token. If the image was uploaded by the same tenant, that should serve to isolate access.","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"0137b7336b8844bd1557f769eaa4d0c98f0fe16b","unresolved":false,"context_lines":[{"line_number":189,"context_line":"The following list of Cyborg properties is not comprehensive. Their usage is"},{"line_number":190,"context_line":"illustrated in the section `Usage in device profiles`_."},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"* ``bitstream_id:\u003cid\u003e``: Specifies the Glance image id of a bitstream."},{"line_number":193,"context_line":""},{"line_number":194,"context_line":"* ``bitstream_at_runtime``: Specifies the need to initiate FPGA programming"},{"line_number":195,"context_line":"  at runtime (see `Use cases`_)."}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_c1954396","line":192,"in_reply_to":"3f79a3b5_82b714d8","updated":"2018-10-05 17:09:21.000000000","message":"The glance images have 4 levels of visibility:\n# openstack image create ... \n[--public | --private | --community | --shared]","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":28766,"name":"Brian Xu","email":"brianx@xilinx.com"},"change_message_id":"0591f9471ff937e72b782c7e66e53dec04b63003","unresolved":false,"context_lines":[{"line_number":189,"context_line":"The following list of Cyborg properties is not comprehensive. Their usage is"},{"line_number":190,"context_line":"illustrated in the section `Usage in device profiles`_."},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"* ``bitstream_id:\u003cid\u003e``: Specifies the Glance image id of a bitstream."},{"line_number":193,"context_line":""},{"line_number":194,"context_line":"* ``bitstream_at_runtime``: Specifies the need to initiate FPGA programming"},{"line_number":195,"context_line":"  at runtime (see `Use cases`_)."}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_fc59e128","line":192,"in_reply_to":"3f79a3b5_e1363fb4","updated":"2018-10-08 16:52:14.000000000","message":"ok, that is good.","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":28766,"name":"Brian Xu","email":"brianx@xilinx.com"},"change_message_id":"c6abbfe97269d3db579760ff777f5d012062841e","unresolved":false,"context_lines":[{"line_number":245,"context_line":"  | trait:CUSTOM_FPGA_REGION_INTEL_\u003cname\u003e\u003drequired"},{"line_number":246,"context_line":"  | accel:bitstream_at_runtime\u003drequired"},{"line_number":247,"context_line":""},{"line_number":248,"context_line":"* Example device profile for AFaaS pre-programmed FPGAs::"},{"line_number":249,"context_line":""},{"line_number":250,"context_line":"  | resources:CUSTOM_ACCELERATOR_FPGA\u003d1"},{"line_number":251,"context_line":"  | trait:CUSTOM_FPGA_INTEL_ARRIA10\u003drequired"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_026b0486","line":248,"updated":"2018-09-26 22:05:25.000000000","message":"I can\u0027t imagine what the use case for this example is for FPGA. For those can be re-programmed, like, bitstream for a function, pre-program is not a good idea. My understanding here is, the fpga driver needs to report what has been pro-programmed, but the driver doesn\u0027t know (actually nobody knows) whether the bitstream is a desired one. AFaaS Orchestration-Programmed is preferred since in this case, cyborg knows what is exactly on the FPGA.\npre-program is good for ASICs","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"0137b7336b8844bd1557f769eaa4d0c98f0fe16b","unresolved":false,"context_lines":[{"line_number":245,"context_line":"  | trait:CUSTOM_FPGA_REGION_INTEL_\u003cname\u003e\u003drequired"},{"line_number":246,"context_line":"  | accel:bitstream_at_runtime\u003drequired"},{"line_number":247,"context_line":""},{"line_number":248,"context_line":"* Example device profile for AFaaS pre-programmed FPGAs::"},{"line_number":249,"context_line":""},{"line_number":250,"context_line":"  | resources:CUSTOM_ACCELERATOR_FPGA\u003d1"},{"line_number":251,"context_line":"  | trait:CUSTOM_FPGA_INTEL_ARRIA10\u003drequired"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_7cb2d498","line":248,"in_reply_to":"3f79a3b5_026b0486","updated":"2018-10-05 17:09:21.000000000","message":"The operator may want to provide a pre-programmed model for many reasons, as stated in Lines 94-102. If the device is an FPGA, this assumes that the specific function in the FPGA can be discovered by the Cyborg driver through some means. \n\nMore broadly, Cyborg provides the same mechanisms to every device type, whether an FPGA or not.","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"ef07b5a045b2d69916008ce68130e91dbb10a383","unresolved":false,"context_lines":[{"line_number":245,"context_line":"  | trait:CUSTOM_FPGA_REGION_INTEL_\u003cname\u003e\u003drequired"},{"line_number":246,"context_line":"  | accel:bitstream_at_runtime\u003drequired"},{"line_number":247,"context_line":""},{"line_number":248,"context_line":"* Example device profile for AFaaS pre-programmed FPGAs::"},{"line_number":249,"context_line":""},{"line_number":250,"context_line":"  | resources:CUSTOM_ACCELERATOR_FPGA\u003d1"},{"line_number":251,"context_line":"  | trait:CUSTOM_FPGA_INTEL_ARRIA10\u003drequired"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_873938a3","line":248,"in_reply_to":"3f79a3b5_4eb3629b","updated":"2018-10-10 23:05:50.000000000","message":"If the Cyborg driver reports a function-id, Cyborg creates a function trait and publishes it. Say there are 2 cards, one with hello-world function H and other with a pre-programmed gzip function G. Cyborg will publish both. However, the operator would have installed device profiles only for the useful functions like G. That device profile will look like this:\n\n{ resources:CUSTOM_ACCELERATOR_FPGA\u003d1\n  trait:CUSTOM_FPGA_FUNCTION_G\u003drequired\n}\n\nThere would be none for H since the operator is not interested in it. But, if he got interested in it for whatever reason, he could create a device profile that references it. Basically, Cyborg gives all the information he needs and he can use it however he wants.\n\nThe aim is to enable devices with minimum configuration; most things are auto-discovered. As you may know, FPGAs are known to be complex to use, and we have a chance to make them operator-friendly. If the operator has to create explicit files listing what functions are allowed, it would be a pain as bitstreams and functions proliferate.\n\nWe may consider a mechanism by which the operator can assign a name to specific function IDs, and that name is used in traits instead of IDs. That can also help address this, since the operator would give a name to G but not to H.","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"01cdd4dec8131ec4e4462f5a774a4561666771ed","unresolved":false,"context_lines":[{"line_number":245,"context_line":"  | trait:CUSTOM_FPGA_REGION_INTEL_\u003cname\u003e\u003drequired"},{"line_number":246,"context_line":"  | accel:bitstream_at_runtime\u003drequired"},{"line_number":247,"context_line":""},{"line_number":248,"context_line":"* Example device profile for AFaaS pre-programmed FPGAs::"},{"line_number":249,"context_line":""},{"line_number":250,"context_line":"  | resources:CUSTOM_ACCELERATOR_FPGA\u003d1"},{"line_number":251,"context_line":"  | trait:CUSTOM_FPGA_INTEL_ARRIA10\u003drequired"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_8657335b","line":248,"in_reply_to":"3f79a3b5_567b13be","updated":"2018-10-09 02:04:03.000000000","message":"Good comments. First, in regular operation, a compute node or an FPGA should not be power-cycled. Only some maintenance operation like FPGA updates should need that.\n\nSecondly, when an FPGA power-cycles, the bitstream is indeed lost but some devices will auto-reload it from flash. If there is a shell logic + user logic, presumably only the shell will be reloaded.Then it is up to the operator to restore the user logic within the maintenance window.\n\nIn some cases, the entire image may be loaded as a unit (there is no shell), so reload from flash is enough. (Just considering all possibilities here.)  \n\nAlso, preprogrammed is a natural milestone of Cyborg development, right? Because the first thing we would do is discover existing functions and use them to launch VMs. Programming with DaaS or AFaaS will be the next step.\n\nRe. #2 in your list, there seems to be a disconnect. Even if a function exists on the card, the device profile may ask for DaaS or AfaaS. Cyborg will support both for any FPGA, and it is up to the operator to define device profiles for specific use cases (DaaS or AFaaS).","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":28766,"name":"Brian Xu","email":"brianx@xilinx.com"},"change_message_id":"0591f9471ff937e72b782c7e66e53dec04b63003","unresolved":false,"context_lines":[{"line_number":245,"context_line":"  | trait:CUSTOM_FPGA_REGION_INTEL_\u003cname\u003e\u003drequired"},{"line_number":246,"context_line":"  | accel:bitstream_at_runtime\u003drequired"},{"line_number":247,"context_line":""},{"line_number":248,"context_line":"* Example device profile for AFaaS pre-programmed FPGAs::"},{"line_number":249,"context_line":""},{"line_number":250,"context_line":"  | resources:CUSTOM_ACCELERATOR_FPGA\u003d1"},{"line_number":251,"context_line":"  | trait:CUSTOM_FPGA_INTEL_ARRIA10\u003drequired"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_567b13be","line":248,"in_reply_to":"3f79a3b5_7cb2d498","updated":"2018-10-08 16:52:14.000000000","message":"For non-fpga, say an asic, the pre-programmed model makes sense. While for fpga, since the bitstream is volatile, which means when there is a power cycle, the bitstream would be lost and have to be reloaded, so maintaining a pre-programmed model is very hard to handle. Imagine some scenarios,\n1. a machine learning bitsteam is pre-programmed, and the driver reports it to cyborg, then the host experiences a power  outage and recovers later, then who will reload the bitstream?\n2. before a host with fpga is online to cyborg, the admin runs a helloworld to verify the fpga is working, then the helloworld bitstream is there and the driver will report there is a \u0027pre-programmed\u0027 bitstream, then this fpga will not be used as DaaS and will be potentially only be used for a helloworld AFaaS. That is, the driver itself has no way knowing whether the exsiting bitstream is a desired one.\n\nSo for fpga, cyborg is the only entrance to load bitstream, and the bitstream loaded by any other means are not accepted and will be ignored by cyborg. The bitstream on fpga and in cyborg db should be consistent. Whenever there is conflict, cyborg db dominates, and the fpga will be reloaded.","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":28766,"name":"Brian Xu","email":"brianx@xilinx.com"},"change_message_id":"014f19f3e2f0c7a55cb7fa77ee67788658073591","unresolved":false,"context_lines":[{"line_number":245,"context_line":"  | trait:CUSTOM_FPGA_REGION_INTEL_\u003cname\u003e\u003drequired"},{"line_number":246,"context_line":"  | accel:bitstream_at_runtime\u003drequired"},{"line_number":247,"context_line":""},{"line_number":248,"context_line":"* Example device profile for AFaaS pre-programmed FPGAs::"},{"line_number":249,"context_line":""},{"line_number":250,"context_line":"  | resources:CUSTOM_ACCELERATOR_FPGA\u003d1"},{"line_number":251,"context_line":"  | trait:CUSTOM_FPGA_INTEL_ARRIA10\u003drequired"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_4eb3629b","line":248,"in_reply_to":"3f79a3b5_8657335b","updated":"2018-10-09 16:34:28.000000000","message":"data center disaster (power outage), though rarely, may still happen. \"operator to restore the user logic within the maintenance window\" in this case, How does an operator easily know what user logic is on the fpga? He needs to query the db, right? This should have been done automatically in my imagination -- when the cyborg driver reports a null bitstream, cyborg will reload with what has been saved in the DB.\n\nRegarding your comments to my #2, I don\u0027t get it. My meaning was, for xilinx fpga, when the fpga device driver and config tool are installed, there are always some built-in test running to verify the fpga is working, such as, a hello-world test, a dma bandwidth test, etc, so besides the shell, there is always a bitstream there already, which does have an id, if a function bitstream is preprogrammed, which has an id also, so when the cyborg drive reports the id, how to know which one is an intentionally preprogrammed?\n\nI didn\u0027t/don\u0027t object to preprogram mode in the spec. My point is, for fpga, it seems not useful. From what I can imagine, in the AFaaS fgpa case, the functions provided are not determined by the discovery, instead, a config file should be provided depending on what kinds of function bitstreams are available in glance, then the bitstream is loaded by cyborg when the vm is launched.","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":28766,"name":"Brian Xu","email":"brianx@xilinx.com"},"change_message_id":"1c81718eed3bc92f00d98137778780116e3b682d","unresolved":false,"context_lines":[{"line_number":245,"context_line":"  | trait:CUSTOM_FPGA_REGION_INTEL_\u003cname\u003e\u003drequired"},{"line_number":246,"context_line":"  | accel:bitstream_at_runtime\u003drequired"},{"line_number":247,"context_line":""},{"line_number":248,"context_line":"* Example device profile for AFaaS pre-programmed FPGAs::"},{"line_number":249,"context_line":""},{"line_number":250,"context_line":"  | resources:CUSTOM_ACCELERATOR_FPGA\u003d1"},{"line_number":251,"context_line":"  | trait:CUSTOM_FPGA_INTEL_ARRIA10\u003drequired"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_8d3959a3","line":248,"in_reply_to":"3f79a3b5_873938a3","updated":"2018-10-11 00:11:04.000000000","message":"when is the device profile installed by the operator?\nIt is highly likely we will be in this situation: \n all fpgas have a function id, some are useful, some are not\n user wants to have a DaaS, I guest cyborg has to get one from those who don\u0027t have useful function id. \u0027useful\u0027 or not is determined by whether a device profile is installed, so depends on when the device profile is installed, the \u0027preprogrammed\u0027 bitstream would be discard for DaaS purpose.\n\nAnother issue is, the reported id is vendor specific, for xilinx, the id has no meaning, so a mapping of the id and the human readable function name must be maintained somewhere. If the driver reports the id first, how does cyborg knows what function it is? If the bitstream is not preprogrammed, cyborg knows the function first, then after driver loads the bitstream, the returned id maps to the function, then cyborg knows the mapping.","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":28766,"name":"Brian Xu","email":"brianx@xilinx.com"},"change_message_id":"c6abbfe97269d3db579760ff777f5d012062841e","unresolved":false,"context_lines":[{"line_number":296,"context_line":""},{"line_number":297,"context_line":"Following changes are needed in Cyborg."},{"line_number":298,"context_line":""},{"line_number":299,"context_line":"* Do not publish PCI functions as resources in Nova. Instead, publish"},{"line_number":300,"context_line":"  RC/RP info to Nova, and keep RP-PCI mapping internally."},{"line_number":301,"context_line":""},{"line_number":302,"context_line":"* Cyborg should associate RPs/RCs and PFs/VFs with Deployables in its"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_e21da810","line":299,"updated":"2018-09-26 22:05:25.000000000","message":"For FPGA runtime programming, after the FPGA function is assigned to vm with pci pass-through, where the mapping of pci address in vm and that in host is saved? I think Nove knows that, does cyborg save that info in its own db?","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"01cdd4dec8131ec4e4462f5a774a4561666771ed","unresolved":false,"context_lines":[{"line_number":296,"context_line":""},{"line_number":297,"context_line":"Following changes are needed in Cyborg."},{"line_number":298,"context_line":""},{"line_number":299,"context_line":"* Do not publish PCI functions as resources in Nova. Instead, publish"},{"line_number":300,"context_line":"  RC/RP info to Nova, and keep RP-PCI mapping internally."},{"line_number":301,"context_line":""},{"line_number":302,"context_line":"* Cyborg should associate RPs/RCs and PFs/VFs with Deployables in its"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_664c57c9","line":299,"in_reply_to":"3f79a3b5_bc4b695c","updated":"2018-10-09 02:04:03.000000000","message":"I don\u0027t have any objection. But we should first define the basics of how run-time programming will work. :)","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":28766,"name":"Brian Xu","email":"brianx@xilinx.com"},"change_message_id":"0591f9471ff937e72b782c7e66e53dec04b63003","unresolved":false,"context_lines":[{"line_number":296,"context_line":""},{"line_number":297,"context_line":"Following changes are needed in Cyborg."},{"line_number":298,"context_line":""},{"line_number":299,"context_line":"* Do not publish PCI functions as resources in Nova. Instead, publish"},{"line_number":300,"context_line":"  RC/RP info to Nova, and keep RP-PCI mapping internally."},{"line_number":301,"context_line":""},{"line_number":302,"context_line":"* Cyborg should associate RPs/RCs and PFs/VFs with Deployables in its"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_bc4b695c","line":299,"in_reply_to":"3f79a3b5_dc19a887","updated":"2018-10-08 16:52:14.000000000","message":"yes, \u0027virsh dump\u0027 equivalent can get that info, then why the info not saved in the cyborg db? otherwise, each bitstream program needs to do the same thing to get the host pci address","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"0137b7336b8844bd1557f769eaa4d0c98f0fe16b","unresolved":false,"context_lines":[{"line_number":296,"context_line":""},{"line_number":297,"context_line":"Following changes are needed in Cyborg."},{"line_number":298,"context_line":""},{"line_number":299,"context_line":"* Do not publish PCI functions as resources in Nova. Instead, publish"},{"line_number":300,"context_line":"  RC/RP info to Nova, and keep RP-PCI mapping internally."},{"line_number":301,"context_line":""},{"line_number":302,"context_line":"* Cyborg should associate RPs/RCs and PFs/VFs with Deployables in its"}],"source_content_type":"text/x-rst","patch_set":1,"id":"3f79a3b5_dc19a887","line":299,"in_reply_to":"3f79a3b5_e21da810","updated":"2018-10-05 17:09:21.000000000","message":"The exact mechanism for run-time programming is not fully agreed upon yet (though I have a proposal). As things stand, Cyborg does not store that mapping, or even discover that for each VM. I don\u0027t know if Nova knows that either -- only the hypervisor like libvirt would know for sure.\n\nCyborg can use \u0027virsh dump xml\u0027 equivalent to find the mapping between VM PCI addresses and host PCI addresses. I don\u0027t know if that works for hypervisors other than libvirt-based ones (KVM, Xen).","commit_id":"21324574b811fcd147da1716b35b726594d0a264"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":82,"context_line":"      is listed only for completeness; this is not going to be addressed"},{"line_number":83,"context_line":"      till the security concerns are fully resolved.)"},{"line_number":84,"context_line":""},{"line_number":85,"context_line":"* Accelerated Function as a Service (AFaaS): The user asks for a function"},{"line_number":86,"context_line":"  (e.g. ipsec) or an algorithm that needs to be offloaded. The accelerator"},{"line_number":87,"context_line":"  containing that function should be assigned to the instance."},{"line_number":88,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_821bbf82","line":85,"range":{"start_line":85,"start_character":2,"end_line":85,"end_character":43},"updated":"2018-10-18 16:00:19.000000000","message":"+1 for the naming :)","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":106,"context_line":""},{"line_number":107,"context_line":"An operator must be able to provide both Device as a Service and Accelerated"},{"line_number":108,"context_line":"Function as a Service in the same cluster."},{"line_number":109,"context_line":""},{"line_number":110,"context_line":"Proposed change"},{"line_number":111,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":112,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_c2121762","line":109,"updated":"2018-10-18 16:00:19.000000000","message":"thanks for the this description is really helps understanding what you are aiming for.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":127,"context_line":"* Each device or a sub-component that contains accelerators is represented"},{"line_number":128,"context_line":"  as a resource provider nested under the compute node (or a NUMA partition"},{"line_number":129,"context_line":"  within the CN). With most devices, there are no sub-components and the"},{"line_number":130,"context_line":"  device itself is the resource provider. This depends on nested RP support"},{"line_number":131,"context_line":"  in Nova [#nRP]_."},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"  * For FPGAs, the device is an RP (nested in the CN RP) and the regions"},{"line_number":134,"context_line":"    within the device will be represented as RPs as well (nested under"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_d5216fa3","line":131,"range":{"start_line":130,"start_character":42,"end_line":131,"end_character":9},"updated":"2018-10-18 16:00:19.000000000","message":"we are pretty close to finish that up so this dependency won\u0027t block you","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":127,"context_line":"* Each device or a sub-component that contains accelerators is represented"},{"line_number":128,"context_line":"  as a resource provider nested under the compute node (or a NUMA partition"},{"line_number":129,"context_line":"  within the CN). With most devices, there are no sub-components and the"},{"line_number":130,"context_line":"  device itself is the resource provider. This depends on nested RP support"},{"line_number":131,"context_line":"  in Nova [#nRP]_."},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"  * For FPGAs, the device is an RP (nested in the CN RP) and the regions"},{"line_number":134,"context_line":"    within the device will be represented as RPs as well (nested under"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_5373301d","line":131,"range":{"start_line":130,"start_character":42,"end_line":131,"end_character":9},"in_reply_to":"3f79a3b5_d5216fa3","updated":"2018-10-19 00:44:00.000000000","message":"Great!","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":133,"context_line":"  * For FPGAs, the device is an RP (nested in the CN RP) and the regions"},{"line_number":134,"context_line":"    within the device will be represented as RPs as well (nested under"},{"line_number":135,"context_line":"    the device RP).  This allows situations where the device may provide"},{"line_number":136,"context_line":"    resources like local memory. This also allows requests that need"},{"line_number":137,"context_line":"    colocation of accelerators in regions in the same device."},{"line_number":138,"context_line":""},{"line_number":139,"context_line":"* Cyborg will associate a Device Type trait with the top-level RP for the"},{"line_number":140,"context_line":"  device which contains accelerators (which is usually the device itself, as"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_152fe789","line":137,"range":{"start_line":136,"start_character":33,"end_line":137,"end_character":61},"updated":"2018-10-18 16:00:19.000000000","message":"I guess that can be done by using the same numbered request group for both devices in the allocation_candidate call.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":133,"context_line":"  * For FPGAs, the device is an RP (nested in the CN RP) and the regions"},{"line_number":134,"context_line":"    within the device will be represented as RPs as well (nested under"},{"line_number":135,"context_line":"    the device RP).  This allows situations where the device may provide"},{"line_number":136,"context_line":"    resources like local memory. This also allows requests that need"},{"line_number":137,"context_line":"    colocation of accelerators in regions in the same device."},{"line_number":138,"context_line":""},{"line_number":139,"context_line":"* Cyborg will associate a Device Type trait with the top-level RP for the"},{"line_number":140,"context_line":"  device which contains accelerators (which is usually the device itself, as"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_931b08ca","line":137,"range":{"start_line":136,"start_character":33,"end_line":137,"end_character":61},"in_reply_to":"3f79a3b5_152fe789","updated":"2018-10-19 00:44:00.000000000","message":"Interesting. Say there is a device (represented as an RP in Placement), and it has two nested children RPs, with traits X and Y resp. Say I want accelerator A with trait X and accelerator B with trait Y, and  want them to be in the same device. If I say this:\n    resources2:accelerator_A\u003d1\n    resources2:accelerator_B\u003d1\n    trait2:X\u003drequired\n    trait2:Y\u003drequired\nwould that work?","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":139,"context_line":"* Cyborg will associate a Device Type trait with the top-level RP for the"},{"line_number":140,"context_line":"  device which contains accelerators (which is usually the device itself, as"},{"line_number":141,"context_line":"  noted). This is of the form CUSTOM_\u003cdevice-type\u003e-\u003cvendor\u003e. E.g."},{"line_number":142,"context_line":"  CUSTOM_GPU_AMD or CUSTOM_FPGA_XILINX. This trait is intended to help match"},{"line_number":143,"context_line":"  the software drivers/libraries in the instance image. It is meant to be used"},{"line_number":144,"context_line":"  in a device profile when a single driver can handle different device"},{"line_number":145,"context_line":"  families."},{"line_number":146,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_3588e369","line":143,"range":{"start_line":142,"start_character":39,"end_line":143,"end_character":55},"updated":"2018-10-18 16:00:19.000000000","message":"Does it meant that the image will specify trait:CUSTOM_GPU_AMD\u003drequired if the image has AMD GPU drivers included?","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":139,"context_line":"* Cyborg will associate a Device Type trait with the top-level RP for the"},{"line_number":140,"context_line":"  device which contains accelerators (which is usually the device itself, as"},{"line_number":141,"context_line":"  noted). This is of the form CUSTOM_\u003cdevice-type\u003e-\u003cvendor\u003e. E.g."},{"line_number":142,"context_line":"  CUSTOM_GPU_AMD or CUSTOM_FPGA_XILINX. This trait is intended to help match"},{"line_number":143,"context_line":"  the software drivers/libraries in the instance image. It is meant to be used"},{"line_number":144,"context_line":"  in a device profile when a single driver can handle different device"},{"line_number":145,"context_line":"  families."},{"line_number":146,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_d3fd003d","line":143,"range":{"start_line":142,"start_character":39,"end_line":143,"end_character":55},"in_reply_to":"3f79a3b5_3588e369","updated":"2018-10-19 00:44:00.000000000","message":"This trait can be specified either in the instance image or in the device profile. \n\nUnfortunately, if the user asks for 2 or more accelerators, using multiple request groups in the device profile, we wouldn\u0027t know which image trait should go with which request group.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":140,"context_line":"  device which contains accelerators (which is usually the device itself, as"},{"line_number":141,"context_line":"  noted). This is of the form CUSTOM_\u003cdevice-type\u003e-\u003cvendor\u003e. E.g."},{"line_number":142,"context_line":"  CUSTOM_GPU_AMD or CUSTOM_FPGA_XILINX. This trait is intended to help match"},{"line_number":143,"context_line":"  the software drivers/libraries in the instance image. It is meant to be used"},{"line_number":144,"context_line":"  in a device profile when a single driver can handle different device"},{"line_number":145,"context_line":"  families."},{"line_number":146,"context_line":""},{"line_number":147,"context_line":"  * For FPGAs, if all the accelerators are inside region(s), only the"},{"line_number":148,"context_line":"    region RPs are annotated with the trait."}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_35b6a327","line":145,"range":{"start_line":143,"start_character":56,"end_line":145,"end_character":11},"updated":"2018-10-18 16:00:19.000000000","message":"You lost me here. How can a device profile support CUSTOM_GPU_AMD and CUTOM_FPGA_XILINX at the same time? I think an example device profile would help me understand this.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":140,"context_line":"  device which contains accelerators (which is usually the device itself, as"},{"line_number":141,"context_line":"  noted). This is of the form CUSTOM_\u003cdevice-type\u003e-\u003cvendor\u003e. E.g."},{"line_number":142,"context_line":"  CUSTOM_GPU_AMD or CUSTOM_FPGA_XILINX. This trait is intended to help match"},{"line_number":143,"context_line":"  the software drivers/libraries in the instance image. It is meant to be used"},{"line_number":144,"context_line":"  in a device profile when a single driver can handle different device"},{"line_number":145,"context_line":"  families."},{"line_number":146,"context_line":""},{"line_number":147,"context_line":"  * For FPGAs, if all the accelerators are inside region(s), only the"},{"line_number":148,"context_line":"    region RPs are annotated with the trait."}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_f356fc2b","line":145,"range":{"start_line":143,"start_character":56,"end_line":145,"end_character":11},"in_reply_to":"3f79a3b5_35b6a327","updated":"2018-10-19 00:44:00.000000000","message":"I should clarify. A single driver may be able to handle multiple GPU types from the same vendor, or multiple FPGA device types from the same vendor.\n\nAs for the device profile, here\u0027s an example (adapted from device profiles spec in the references below):\n\n{\n    \u0027version\u0027: 1.0,\n    \u0027groups\u0027: [\n      { \u0027resources:CUSTOM_ACCELERATOR_GPU\u003d2\u0027,\n        \u0027trait:CUSTOM_GPU_AMD\u003drequired\u0027,\n        \u0027accel:video_ram\u003d2GB\u0027\n      }\n    ]\n}\n\nThis is a request for 2 GPU accelerators, but only the vendor name trait is applied.\n\nOn another note, I am thinking of removing this from the list on the grounds that it is easier to add a trait than to remove an existing one. Besides, we have a provision for custom traits that a Cyborg driver can provide, and drivers can choose to pass this trait.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":144,"context_line":"  in a device profile when a single driver can handle different device"},{"line_number":145,"context_line":"  families."},{"line_number":146,"context_line":""},{"line_number":147,"context_line":"  * For FPGAs, if all the accelerators are inside region(s), only the"},{"line_number":148,"context_line":"    region RPs are annotated with the trait."},{"line_number":149,"context_line":""},{"line_number":150,"context_line":"* Cyborg will associate a Device Family trait with each device as"},{"line_number":151,"context_line":"  needed, of the form CUSTOM_\u003cdevice-type\u003e_\u003cvendor\u003e_\u003cfamily\u003e."}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_155da715","line":148,"range":{"start_line":147,"start_character":3,"end_line":148,"end_character":44},"updated":"2018-10-18 16:00:19.000000000","message":"Does it mean that the trait will be on the leaf of the FPGA RP tree or that it will be on the FPGA RP and under that there will be region RPs without the trait?","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":144,"context_line":"  in a device profile when a single driver can handle different device"},{"line_number":145,"context_line":"  families."},{"line_number":146,"context_line":""},{"line_number":147,"context_line":"  * For FPGAs, if all the accelerators are inside region(s), only the"},{"line_number":148,"context_line":"    region RPs are annotated with the trait."},{"line_number":149,"context_line":""},{"line_number":150,"context_line":"* Cyborg will associate a Device Family trait with each device as"},{"line_number":151,"context_line":"  needed, of the form CUSTOM_\u003cdevice-type\u003e_\u003cvendor\u003e_\u003cfamily\u003e."}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_3e70bba7","line":148,"range":{"start_line":147,"start_character":3,"end_line":148,"end_character":44},"in_reply_to":"3f79a3b5_155da715","updated":"2018-10-19 00:44:00.000000000","message":"This says that the traits are applied on the leaf nodes only.\n\nWhat makes sense for the use case where the user wants two accelerators to be co-located on the same device?","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":146,"context_line":""},{"line_number":147,"context_line":"  * For FPGAs, if all the accelerators are inside region(s), only the"},{"line_number":148,"context_line":"    region RPs are annotated with the trait."},{"line_number":149,"context_line":""},{"line_number":150,"context_line":"* Cyborg will associate a Device Family trait with each device as"},{"line_number":151,"context_line":"  needed, of the form CUSTOM_\u003cdevice-type\u003e_\u003cvendor\u003e_\u003cfamily\u003e."},{"line_number":152,"context_line":"  E.g. CUSTOM_GPU_AMD_RADEON_R9 or CUSTOM_FPGA_INTEL_ARRIA10."}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_35af83e1","line":149,"updated":"2018-10-18 16:00:19.000000000","message":"In general I suggest to draw an example RP tree in the spec as that helps understanding the proposed model.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":146,"context_line":""},{"line_number":147,"context_line":"  * For FPGAs, if all the accelerators are inside region(s), only the"},{"line_number":148,"context_line":"    region RPs are annotated with the trait."},{"line_number":149,"context_line":""},{"line_number":150,"context_line":"* Cyborg will associate a Device Family trait with each device as"},{"line_number":151,"context_line":"  needed, of the form CUSTOM_\u003cdevice-type\u003e_\u003cvendor\u003e_\u003cfamily\u003e."},{"line_number":152,"context_line":"  E.g. CUSTOM_GPU_AMD_RADEON_R9 or CUSTOM_FPGA_INTEL_ARRIA10."}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_bea84bda","line":149,"in_reply_to":"3f79a3b5_35af83e1","updated":"2018-10-19 00:44:00.000000000","message":"Sure. I may have to revise this proposal based on your feedback. I will draw up a diagram after that revision.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":147,"context_line":"  * For FPGAs, if all the accelerators are inside region(s), only the"},{"line_number":148,"context_line":"    region RPs are annotated with the trait."},{"line_number":149,"context_line":""},{"line_number":150,"context_line":"* Cyborg will associate a Device Family trait with each device as"},{"line_number":151,"context_line":"  needed, of the form CUSTOM_\u003cdevice-type\u003e_\u003cvendor\u003e_\u003cfamily\u003e."},{"line_number":152,"context_line":"  E.g. CUSTOM_GPU_AMD_RADEON_R9 or CUSTOM_FPGA_INTEL_ARRIA10."},{"line_number":153,"context_line":"  This is not a product name, but the name of a device family, used to"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_b53f1385","line":150,"range":{"start_line":150,"start_character":46,"end_line":150,"end_character":62},"updated":"2018-10-18 16:00:19.000000000","message":"with each device RP?","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":147,"context_line":"  * For FPGAs, if all the accelerators are inside region(s), only the"},{"line_number":148,"context_line":"    region RPs are annotated with the trait."},{"line_number":149,"context_line":""},{"line_number":150,"context_line":"* Cyborg will associate a Device Family trait with each device as"},{"line_number":151,"context_line":"  needed, of the form CUSTOM_\u003cdevice-type\u003e_\u003cvendor\u003e_\u003cfamily\u003e."},{"line_number":152,"context_line":"  E.g. CUSTOM_GPU_AMD_RADEON_R9 or CUSTOM_FPGA_INTEL_ARRIA10."},{"line_number":153,"context_line":"  This is not a product name, but the name of a device family, used to"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_feec8329","line":150,"range":{"start_line":150,"start_character":46,"end_line":150,"end_character":62},"in_reply_to":"3f79a3b5_b53f1385","updated":"2018-10-19 00:44:00.000000000","message":"Yes.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":167,"context_line":"* For FPGAs, Cyborg may associate a function type trait with a region"},{"line_number":168,"context_line":"  when the region gets programmed, of the form"},{"line_number":169,"context_line":"  CUSTOM_FPGA_FUNCTION_\u003cvendor\u003e_\u003cid-string\u003e. E.g."},{"line_number":170,"context_line":"  CUSTOM_FPGA_FUNCTION_INTEL_\u003cgzip-id\u003e. This is needed for AFaaS use case."},{"line_number":171,"context_line":""},{"line_number":172,"context_line":"Cyborg properties"},{"line_number":173,"context_line":"-----------------"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_b5b4f3f2","line":170,"updated":"2018-10-18 16:00:19.000000000","message":"Does it true that the end user does not need know the \u003cgzip-id\u003e to get such a function i her server, instead she has to select a device profile from Cyborg API with an understandable name?","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":167,"context_line":"* For FPGAs, Cyborg may associate a function type trait with a region"},{"line_number":168,"context_line":"  when the region gets programmed, of the form"},{"line_number":169,"context_line":"  CUSTOM_FPGA_FUNCTION_\u003cvendor\u003e_\u003cid-string\u003e. E.g."},{"line_number":170,"context_line":"  CUSTOM_FPGA_FUNCTION_INTEL_\u003cgzip-id\u003e. This is needed for AFaaS use case."},{"line_number":171,"context_line":""},{"line_number":172,"context_line":"Cyborg properties"},{"line_number":173,"context_line":"-----------------"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_ded3c762","line":170,"in_reply_to":"3f79a3b5_b5b4f3f2","updated":"2018-10-19 00:44:00.000000000","message":"Yes. Only the operator needs to know the gzip-id. We will hopefully define a way to provide names to operators as well.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":174,"context_line":"In addition to the traits, user requests for accelerators may include"},{"line_number":175,"context_line":"Cyborg-specific properties in the device profile. These are not interpreted"},{"line_number":176,"context_line":"by Nova. However, they may specify other details such as which bitstreams"},{"line_number":177,"context_line":"are needed."},{"line_number":178,"context_line":""},{"line_number":179,"context_line":"When the device profile is translated by Cyborg into extra specs to be added"},{"line_number":180,"context_line":"to the flavor, the Cyborg properties will be prefixed with the keyword"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_957d3720","line":177,"updated":"2018-10-18 16:00:19.000000000","message":"I guess nova only sees a device_profile_uuid in the server create request and then nova reads the device_profile entity from the Cyborg API and that entity might contain more fields than nova needs but nova will only use the ones needed to generate a proper placement allocation_candidate query.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":174,"context_line":"In addition to the traits, user requests for accelerators may include"},{"line_number":175,"context_line":"Cyborg-specific properties in the device profile. These are not interpreted"},{"line_number":176,"context_line":"by Nova. However, they may specify other details such as which bitstreams"},{"line_number":177,"context_line":"are needed."},{"line_number":178,"context_line":""},{"line_number":179,"context_line":"When the device profile is translated by Cyborg into extra specs to be added"},{"line_number":180,"context_line":"to the flavor, the Cyborg properties will be prefixed with the keyword"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_1e0e1fe4","line":177,"in_reply_to":"3f79a3b5_957d3720","updated":"2018-10-19 00:44:00.000000000","message":"1. There is a device profile name in the server create request (as part of the flavor in Phase 1, as stated in Nova spec).\n2. It was originally proposed that Cyborg properties will be returned to Nova as part of the device profile, to be stored with the request groups. However, the review of the Nova spec(https://review.openstack.org/#/c/603955/), that was rejected. So, the revised proposal is to not send Cyborg properties with the device profile to Nova.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":176,"context_line":"by Nova. However, they may specify other details such as which bitstreams"},{"line_number":177,"context_line":"are needed."},{"line_number":178,"context_line":""},{"line_number":179,"context_line":"When the device profile is translated by Cyborg into extra specs to be added"},{"line_number":180,"context_line":"to the flavor, the Cyborg properties will be prefixed with the keyword"},{"line_number":181,"context_line":"``accel:`` in the extra specs. In the granular request syntax, it would be"},{"line_number":182,"context_line":"suffixed with the request group number, like ``accelN:``."},{"line_number":183,"context_line":""},{"line_number":184,"context_line":"The Cyborg properties will initially be used for specifying"},{"line_number":185,"context_line":"device-type-specific constructs like bitstreams. However, in the future,"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_35a3039e","line":182,"range":{"start_line":179,"start_character":0,"end_line":182,"end_character":57},"updated":"2018-10-18 16:00:19.000000000","message":"Why do we need to translate the resource request from a device profiles into the Nova flavor? In the bandwidth case nova reads the resource request from the neutron port and puts that into the RequestSpec object internally.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":176,"context_line":"by Nova. However, they may specify other details such as which bitstreams"},{"line_number":177,"context_line":"are needed."},{"line_number":178,"context_line":""},{"line_number":179,"context_line":"When the device profile is translated by Cyborg into extra specs to be added"},{"line_number":180,"context_line":"to the flavor, the Cyborg properties will be prefixed with the keyword"},{"line_number":181,"context_line":"``accel:`` in the extra specs. In the granular request syntax, it would be"},{"line_number":182,"context_line":"suffixed with the request group number, like ``accelN:``."},{"line_number":183,"context_line":""},{"line_number":184,"context_line":"The Cyborg properties will initially be used for specifying"},{"line_number":185,"context_line":"device-type-specific constructs like bitstreams. However, in the future,"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_deef47f8","line":182,"range":{"start_line":179,"start_character":0,"end_line":182,"end_character":57},"in_reply_to":"3f79a3b5_35a3039e","updated":"2018-10-19 00:44:00.000000000","message":"My bad. Will rewrite.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":186,"context_line":"Cyborg may provide filters and weighers that use these properties to influence"},{"line_number":187,"context_line":"scheduling."},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"The following list of Cyborg properties is not comprehensive. Their usage is"},{"line_number":190,"context_line":"illustrated in the section `Usage in device profiles`_."},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"* ``bitstream_id:\u003cid\u003e``: Specifies the Glance image id of a bitstream."}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_d5ff2f67","line":189,"range":{"start_line":189,"start_character":40,"end_line":189,"end_character":60},"updated":"2018-10-18 16:00:19.000000000","message":"I think as neither nova nor placement uses them it doesn\u0027t need to be listed in this spec.\n--later--\nohh so I guess it is here to allow for a meaningful usage example below. Then I\u0027m OK with it.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":186,"context_line":"Cyborg may provide filters and weighers that use these properties to influence"},{"line_number":187,"context_line":"scheduling."},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"The following list of Cyborg properties is not comprehensive. Their usage is"},{"line_number":190,"context_line":"illustrated in the section `Usage in device profiles`_."},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"* ``bitstream_id:\u003cid\u003e``: Specifies the Glance image id of a bitstream."}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_1e27ff65","line":189,"range":{"start_line":189,"start_character":40,"end_line":189,"end_character":60},"in_reply_to":"3f79a3b5_d5ff2f67","updated":"2018-10-19 00:44:00.000000000","message":"This is a Cyborg spec, not a Nova spec. :) The Nova spec https://review.openstack.org/#/c/603955/ is the over-arching spec, that refers to Cyborg specs, such as this one, for the details. Please review that too.\n\nSpecifically, this spec addresses only the representation in Placement: the modeling of RPs, traits, etc., and how they can be related to the use cases of interest.\n\nThese properties are listed here only for the examples, as you said. I could refer to the device profiles spec. I also need to  update the examples.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":195,"context_line":"  at runtime (see `Use cases`_)."},{"line_number":196,"context_line":""},{"line_number":197,"context_line":"* ``function_id:\u003cid\u003e``: Specifies the function id in situations where"},{"line_number":198,"context_line":"  preferred traits are called for, unti Nova provides preferred traits. (See"},{"line_number":199,"context_line":"  AFaaS orchestration-programmed example in next section.)"},{"line_number":200,"context_line":""},{"line_number":201,"context_line":"* ``function_name:\u003cname\u003e``: Specifies the function by name. Issues of who"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_7535fb42","line":198,"range":{"start_line":198,"start_character":35,"end_line":198,"end_character":39},"updated":"2018-10-18 16:00:19.000000000","message":"nit: until?","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":195,"context_line":"  at runtime (see `Use cases`_)."},{"line_number":196,"context_line":""},{"line_number":197,"context_line":"* ``function_id:\u003cid\u003e``: Specifies the function id in situations where"},{"line_number":198,"context_line":"  preferred traits are called for, unti Nova provides preferred traits. (See"},{"line_number":199,"context_line":"  AFaaS orchestration-programmed example in next section.)"},{"line_number":200,"context_line":""},{"line_number":201,"context_line":"* ``function_name:\u003cname\u003e``: Specifies the function by name. Issues of who"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_dec6676a","line":198,"range":{"start_line":198,"start_character":35,"end_line":198,"end_character":39},"in_reply_to":"3f79a3b5_7535fb42","updated":"2018-10-19 00:44:00.000000000","message":"Done","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":306,"context_line":"  RCs can be created."},{"line_number":307,"context_line":""},{"line_number":308,"context_line":"* Deployables table should track which RP corresponds to each Deployable."},{"line_number":309,"context_line":""},{"line_number":310,"context_line":"REST API impact"},{"line_number":311,"context_line":"---------------"},{"line_number":312,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_15f7e75c","line":309,"updated":"2018-10-18 16:00:19.000000000","message":"This section should detail what data model change are needed in Nova and or Placement","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":306,"context_line":"  RCs can be created."},{"line_number":307,"context_line":""},{"line_number":308,"context_line":"* Deployables table should track which RP corresponds to each Deployable."},{"line_number":309,"context_line":""},{"line_number":310,"context_line":"REST API impact"},{"line_number":311,"context_line":"---------------"},{"line_number":312,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_9ec0ef4c","line":309,"in_reply_to":"3f79a3b5_15f7e75c","updated":"2018-10-19 00:44:00.000000000","message":"That is done in the Nova spec https://review.openstack.org/#/c/603955/.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":9708,"name":"Balazs Gibizer","display_name":"gibi","email":"gibizer@gmail.com","username":"gibi"},"change_message_id":"084a3b6116ca751a4723d72486b6e929a05c7445","unresolved":false,"context_lines":[{"line_number":362,"context_line":"Work Items"},{"line_number":363,"context_line":"----------"},{"line_number":364,"context_line":""},{"line_number":365,"context_line":"The code changes needed to realize this device representation are described in"},{"line_number":366,"context_line":"other specs. Work items are stated in those specs."},{"line_number":367,"context_line":""},{"line_number":368,"context_line":"Dependencies"},{"line_number":369,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_55ab1f1e","line":366,"range":{"start_line":365,"start_character":0,"end_line":366,"end_character":50},"updated":"2018-10-18 16:00:19.000000000","message":"So this spec does not suggest any code changes in nova or placement?","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"e7ace88dea5458553e5abd45d88a63b45f97d6d2","unresolved":false,"context_lines":[{"line_number":362,"context_line":"Work Items"},{"line_number":363,"context_line":"----------"},{"line_number":364,"context_line":""},{"line_number":365,"context_line":"The code changes needed to realize this device representation are described in"},{"line_number":366,"context_line":"other specs. Work items are stated in those specs."},{"line_number":367,"context_line":""},{"line_number":368,"context_line":"Dependencies"},{"line_number":369,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3f79a3b5_fea483ba","line":366,"range":{"start_line":365,"start_character":0,"end_line":366,"end_character":50},"in_reply_to":"3f79a3b5_55ab1f1e","updated":"2018-10-19 00:44:00.000000000","message":"That is done in the Nova spec https://review.openstack.org/#/c/603955/.","commit_id":"71709480159817f88d3adf44f79caedf4f27163e"}],"specs/train/approved/cyborg-nova-placement.rst":[{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"e13399608c226c13e3c79edcd52a90f5446c3dde","unresolved":false,"context_lines":[{"line_number":32,"context_line":"* Accelerator: The unit that can be assigned to an instance for offloading"},{"line_number":33,"context_line":"  specific functionality. For non-FPGA devices, it is either the device itself"},{"line_number":34,"context_line":"  or a virtualized version of it (e.g. vGPUs). For FPGAs, an accelerator is"},{"line_number":35,"context_line":"  either the entire device, a region within the device or a function."},{"line_number":36,"context_line":""},{"line_number":37,"context_line":"* Bitstream: An FPGA image, usually a binary file, possibly with"},{"line_number":38,"context_line":"  vendor-specific metadata. A bitstream may implement one or more functions."}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_f16cc19d","line":35,"range":{"start_line":35,"start_character":58,"end_line":35,"end_character":68},"updated":"2019-07-05 08:03:50.000000000","message":"s/function/virtual function.","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"cc7fa7c49feda3f76eb7e121b7dd34f903da79be","unresolved":false,"context_lines":[{"line_number":32,"context_line":"* Accelerator: The unit that can be assigned to an instance for offloading"},{"line_number":33,"context_line":"  specific functionality. For non-FPGA devices, it is either the device itself"},{"line_number":34,"context_line":"  or a virtualized version of it (e.g. vGPUs). For FPGAs, an accelerator is"},{"line_number":35,"context_line":"  either the entire device, a region within the device or a function."},{"line_number":36,"context_line":""},{"line_number":37,"context_line":"* Bitstream: An FPGA image, usually a binary file, possibly with"},{"line_number":38,"context_line":"  vendor-specific metadata. A bitstream may implement one or more functions."}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_d662c516","line":35,"range":{"start_line":35,"start_character":58,"end_line":35,"end_character":68},"in_reply_to":"7faddb67_f16cc19d","updated":"2019-07-08 03:41:51.000000000","message":"I mean an algorithm to be offloaded, such as an AFU_ID for Intel. Not a PCI function.","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"e13399608c226c13e3c79edcd52a90f5446c3dde","unresolved":false,"context_lines":[{"line_number":59,"context_line":"(VF)."},{"line_number":60,"context_line":""},{"line_number":61,"context_line":"A device may have components, such as flash memory or BMC, which are not of"},{"line_number":62,"context_line":"relevance to Nova or Placement. Those components may have attributes, such as"},{"line_number":63,"context_line":"flash memory capacity or BMC firmware version."},{"line_number":64,"context_line":""},{"line_number":65,"context_line":"This is diagrammatically shown below::"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_d403b30c","line":62,"range":{"start_line":62,"start_character":58,"end_line":62,"end_character":68},"updated":"2019-07-05 08:03:50.000000000","message":"The attribute you mentioned here is not the attribute associated with deployable, is it?  How Cyborg handle thest components.","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"b20a8a90c1c589a0d8eead048c0f3e21fcec6120","unresolved":false,"context_lines":[{"line_number":59,"context_line":"(VF)."},{"line_number":60,"context_line":""},{"line_number":61,"context_line":"A device may have components, such as flash memory or BMC, which are not of"},{"line_number":62,"context_line":"relevance to Nova or Placement. Those components may have attributes, such as"},{"line_number":63,"context_line":"flash memory capacity or BMC firmware version."},{"line_number":64,"context_line":""},{"line_number":65,"context_line":"This is diagrammatically shown below::"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_6b57115a","line":62,"range":{"start_line":62,"start_character":58,"end_line":62,"end_character":68},"in_reply_to":"7faddb67_5b335dac","updated":"2019-07-12 08:54:08.000000000","message":"Yes.","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"d3f0e9f2fddc2a86ac9bab63ea71fc6287c3a608","unresolved":false,"context_lines":[{"line_number":59,"context_line":"(VF)."},{"line_number":60,"context_line":""},{"line_number":61,"context_line":"A device may have components, such as flash memory or BMC, which are not of"},{"line_number":62,"context_line":"relevance to Nova or Placement. Those components may have attributes, such as"},{"line_number":63,"context_line":"flash memory capacity or BMC firmware version."},{"line_number":64,"context_line":""},{"line_number":65,"context_line":"This is diagrammatically shown below::"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_5b335dac","line":62,"range":{"start_line":62,"start_character":58,"end_line":62,"end_character":68},"in_reply_to":"7faddb67_966c4d09","updated":"2019-07-08 06:18:16.000000000","message":"Thanks for your explanation, as my understanding, there is no requirement about report these kinds of resources to placement, right?","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"cc7fa7c49feda3f76eb7e121b7dd34f903da79be","unresolved":false,"context_lines":[{"line_number":59,"context_line":"(VF)."},{"line_number":60,"context_line":""},{"line_number":61,"context_line":"A device may have components, such as flash memory or BMC, which are not of"},{"line_number":62,"context_line":"relevance to Nova or Placement. Those components may have attributes, such as"},{"line_number":63,"context_line":"flash memory capacity or BMC firmware version."},{"line_number":64,"context_line":""},{"line_number":65,"context_line":"This is diagrammatically shown below::"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_966c4d09","line":62,"range":{"start_line":62,"start_character":58,"end_line":62,"end_character":68},"in_reply_to":"7faddb67_d403b30c","updated":"2019-07-08 03:41:51.000000000","message":"Yes, these are device attributes, not deployable attributes. We have the *_board_info fields in the device object for this. [1]\n\n[1] https://opendev.org/openstack/cyborg/src/branch/master/cyborg/objects/driver_objects/driver_device.py#L38","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"e13399608c226c13e3c79edcd52a90f5446c3dde","unresolved":false,"context_lines":[{"line_number":142,"context_line":"  been proposed for GPUs and FPGAs: ACCELERATOR_GPU and ACCELERATOR_FPGA"},{"line_number":143,"context_line":"  [#std-names]_. For others, Cyborg will create custom RCs of the form"},{"line_number":144,"context_line":"  CUSTOM_ACCELERATOR_\u003cdevice-type\u003e. E.g. CUSTOM_ACCELERATOR_AICHIP."},{"line_number":145,"context_line":"  Uisng a different RC for each device type helps in defining separate"},{"line_number":146,"context_line":"  quotas for different device types."},{"line_number":147,"context_line":""},{"line_number":148,"context_line":"  * Note that an accelerator is not an object, either in Cyborg or in"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_af8ee024","line":145,"range":{"start_line":145,"start_character":2,"end_line":145,"end_character":7},"updated":"2019-07-05 08:03:50.000000000","message":"Using","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"cc7fa7c49feda3f76eb7e121b7dd34f903da79be","unresolved":false,"context_lines":[{"line_number":142,"context_line":"  been proposed for GPUs and FPGAs: ACCELERATOR_GPU and ACCELERATOR_FPGA"},{"line_number":143,"context_line":"  [#std-names]_. For others, Cyborg will create custom RCs of the form"},{"line_number":144,"context_line":"  CUSTOM_ACCELERATOR_\u003cdevice-type\u003e. E.g. CUSTOM_ACCELERATOR_AICHIP."},{"line_number":145,"context_line":"  Uisng a different RC for each device type helps in defining separate"},{"line_number":146,"context_line":"  quotas for different device types."},{"line_number":147,"context_line":""},{"line_number":148,"context_line":"  * Note that an accelerator is not an object, either in Cyborg or in"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_d87af322","line":145,"range":{"start_line":145,"start_character":2,"end_line":145,"end_character":7},"in_reply_to":"7faddb67_af8ee024","updated":"2019-07-08 03:41:51.000000000","message":"Done","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"e13399608c226c13e3c79edcd52a90f5446c3dde","unresolved":false,"context_lines":[{"line_number":162,"context_line":"  Each accelerator in that deployable is represented as an inventory of the"},{"line_number":163,"context_line":"  corresponding RP."},{"line_number":164,"context_line":""},{"line_number":165,"context_line":"* Cyborg will associate a Device Family trait with each device as"},{"line_number":166,"context_line":"  needed, of the form CUSTOM_\u003cdevice-type\u003e_\u003cvendor\u003e_\u003cfamily\u003e."},{"line_number":167,"context_line":"  E.g. CUSTOM_GPU_AMD_RADEON_R9 or CUSTOM_FPGA_INTEL_ARRIA10."},{"line_number":168,"context_line":"  This is not a product name, but the name of a device family, used to"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_6fb1c8e1","line":165,"range":{"start_line":165,"start_character":56,"end_line":165,"end_character":62},"updated":"2019-07-05 08:03:50.000000000","message":"s/device/deployable, the attribute_list is a field of deployable, the trait is associated with RP(deployable).","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"cc7fa7c49feda3f76eb7e121b7dd34f903da79be","unresolved":false,"context_lines":[{"line_number":162,"context_line":"  Each accelerator in that deployable is represented as an inventory of the"},{"line_number":163,"context_line":"  corresponding RP."},{"line_number":164,"context_line":""},{"line_number":165,"context_line":"* Cyborg will associate a Device Family trait with each device as"},{"line_number":166,"context_line":"  needed, of the form CUSTOM_\u003cdevice-type\u003e_\u003cvendor\u003e_\u003cfamily\u003e."},{"line_number":167,"context_line":"  E.g. CUSTOM_GPU_AMD_RADEON_R9 or CUSTOM_FPGA_INTEL_ARRIA10."},{"line_number":168,"context_line":"  This is not a product name, but the name of a device family, used to"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_78773f3c","line":165,"range":{"start_line":165,"start_character":56,"end_line":165,"end_character":62},"in_reply_to":"7faddb67_6fb1c8e1","updated":"2019-07-08 03:41:51.000000000","message":"Done","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"e13399608c226c13e3c79edcd52a90f5446c3dde","unresolved":false,"context_lines":[{"line_number":168,"context_line":"  This is not a product name, but the name of a device family, used to"},{"line_number":169,"context_line":"  match software in the instance image with the device family."},{"line_number":170,"context_line":""},{"line_number":171,"context_line":"* For FPGAs, Cyborg will associate a region type trait with each region"},{"line_number":172,"context_line":"  (or with the FPGA itself if there is no Partial Reconfiguration"},{"line_number":173,"context_line":"  support), of the form CUSTOM_FPGA_REGION_\u003cvendor\u003e_\u003cid-string\u003e."},{"line_number":174,"context_line":"  E.g.  CUSTOM_FPGA_REGION_INTEL_\u003cid-string\u003e. This is needed for Device"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_6fe6a8eb","line":171,"range":{"start_line":171,"start_character":13,"end_line":171,"end_character":49},"updated":"2019-07-05 08:03:50.000000000","message":"If there is no partial reconfiguration support, I think we can just ignore the region trait. This trait will be useless.  This can be done in driver layer, driver will check if the FPGA card support partial reconfiguration or not. If it\u0027s supported, driver will fill attribute list with CUSTOM_FPGA_REGION_xxx, otherwise it will not fill region related trait.","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"cc7fa7c49feda3f76eb7e121b7dd34f903da79be","unresolved":false,"context_lines":[{"line_number":168,"context_line":"  This is not a product name, but the name of a device family, used to"},{"line_number":169,"context_line":"  match software in the instance image with the device family."},{"line_number":170,"context_line":""},{"line_number":171,"context_line":"* For FPGAs, Cyborg will associate a region type trait with each region"},{"line_number":172,"context_line":"  (or with the FPGA itself if there is no Partial Reconfiguration"},{"line_number":173,"context_line":"  support), of the form CUSTOM_FPGA_REGION_\u003cvendor\u003e_\u003cid-string\u003e."},{"line_number":174,"context_line":"  E.g.  CUSTOM_FPGA_REGION_INTEL_\u003cid-string\u003e. This is needed for Device"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_b64aa97d","line":171,"range":{"start_line":171,"start_character":13,"end_line":171,"end_character":49},"in_reply_to":"7faddb67_6fe6a8eb","updated":"2019-07-08 03:41:51.000000000","message":"I agree the term \u0027region type\u0027 can be confusing but, when there is no PR, we treat the whole FPGA as a single region.\n\nThis trait will always be needed, even for FPGAs without PR, because there needs to be a way to express bitstream compatibility for that FPGA. That is, bitstreams for that FPGA will have metadata saying that they are synthesized for the \u0027region type\u0027 of that whole FPGA.","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"b20a8a90c1c589a0d8eead048c0f3e21fcec6120","unresolved":false,"context_lines":[{"line_number":168,"context_line":"  This is not a product name, but the name of a device family, used to"},{"line_number":169,"context_line":"  match software in the instance image with the device family."},{"line_number":170,"context_line":""},{"line_number":171,"context_line":"* For FPGAs, Cyborg will associate a region type trait with each region"},{"line_number":172,"context_line":"  (or with the FPGA itself if there is no Partial Reconfiguration"},{"line_number":173,"context_line":"  support), of the form CUSTOM_FPGA_REGION_\u003cvendor\u003e_\u003cid-string\u003e."},{"line_number":174,"context_line":"  E.g.  CUSTOM_FPGA_REGION_INTEL_\u003cid-string\u003e. This is needed for Device"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_0bce9d2d","line":171,"range":{"start_line":171,"start_character":13,"end_line":171,"end_character":49},"in_reply_to":"7faddb67_9bed55f1","updated":"2019-07-12 08:54:08.000000000","message":"Yes, it looks like CUSTOM_FPGA_REGION_INTEL_9926AB6D6C925A68AABCA7D84C545738. (The setup scripts in the pilot code do this, but they don\u0027t include INTEL - that needs change.) \n\nFor Intel, we get that id from /sys/class/fpga/intel-fpga-dev.0/intel-fpga-fme.0/pr/interface_id.","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"d3f0e9f2fddc2a86ac9bab63ea71fc6287c3a608","unresolved":false,"context_lines":[{"line_number":168,"context_line":"  This is not a product name, but the name of a device family, used to"},{"line_number":169,"context_line":"  match software in the instance image with the device family."},{"line_number":170,"context_line":""},{"line_number":171,"context_line":"* For FPGAs, Cyborg will associate a region type trait with each region"},{"line_number":172,"context_line":"  (or with the FPGA itself if there is no Partial Reconfiguration"},{"line_number":173,"context_line":"  support), of the form CUSTOM_FPGA_REGION_\u003cvendor\u003e_\u003cid-string\u003e."},{"line_number":174,"context_line":"  E.g.  CUSTOM_FPGA_REGION_INTEL_\u003cid-string\u003e. This is needed for Device"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_9bed55f1","line":171,"range":{"start_line":171,"start_character":13,"end_line":171,"end_character":49},"in_reply_to":"7faddb67_b64aa97d","updated":"2019-07-08 06:18:16.000000000","message":"Agree, could you give me an example of region traits. I can add it in placement report patch, like CUSTOM_FPGA_REGION_INTEL_1? Where does the id_string come from?","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"e13399608c226c13e3c79edcd52a90f5446c3dde","unresolved":false,"context_lines":[{"line_number":274,"context_line":"* Do not publish PCI functions as resources in Nova. Instead, publish"},{"line_number":275,"context_line":"  RC/RP info to Nova, and keep RP-PCI mapping internally."},{"line_number":276,"context_line":""},{"line_number":277,"context_line":"* Cyborg should associate RPs/RCs and PFs/VFs with Deployables in its"},{"line_number":278,"context_line":"  internal DB."},{"line_number":279,"context_line":""},{"line_number":280,"context_line":"* Driver/agent interface needs to report device/region types so that"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_afc6e015","line":277,"range":{"start_line":277,"start_character":15,"end_line":277,"end_character":62},"updated":"2019-07-05 08:03:50.000000000","message":"This point has no relation with my placement report code. Just curious about why we should do this, placement knows this mapping relation. We can update the num_accelerators during attachment. And I remember there is no field describes RP or RC in deployable table.","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"cc7fa7c49feda3f76eb7e121b7dd34f903da79be","unresolved":false,"context_lines":[{"line_number":274,"context_line":"* Do not publish PCI functions as resources in Nova. Instead, publish"},{"line_number":275,"context_line":"  RC/RP info to Nova, and keep RP-PCI mapping internally."},{"line_number":276,"context_line":""},{"line_number":277,"context_line":"* Cyborg should associate RPs/RCs and PFs/VFs with Deployables in its"},{"line_number":278,"context_line":"  internal DB."},{"line_number":279,"context_line":""},{"line_number":280,"context_line":"* Driver/agent interface needs to report device/region types so that"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_b8405737","line":277,"range":{"start_line":277,"start_character":15,"end_line":277,"end_character":62},"in_reply_to":"7faddb67_afc6e015","updated":"2019-07-08 03:41:51.000000000","message":"On reprogramming, Cyborg would need to remove the trait for the previous function id. How would Cyborg do what that previous function id is? It could query Placement and look for \u0027CUSTOM_FUNCTON_*\u0027 but a better solution is to keep it as an attribute for the deployable.","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"d3f0e9f2fddc2a86ac9bab63ea71fc6287c3a608","unresolved":false,"context_lines":[{"line_number":274,"context_line":"* Do not publish PCI functions as resources in Nova. Instead, publish"},{"line_number":275,"context_line":"  RC/RP info to Nova, and keep RP-PCI mapping internally."},{"line_number":276,"context_line":""},{"line_number":277,"context_line":"* Cyborg should associate RPs/RCs and PFs/VFs with Deployables in its"},{"line_number":278,"context_line":"  internal DB."},{"line_number":279,"context_line":""},{"line_number":280,"context_line":"* Driver/agent interface needs to report device/region types so that"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_bbcff17d","line":277,"range":{"start_line":277,"start_character":15,"end_line":277,"end_character":62},"in_reply_to":"7faddb67_b8405737","updated":"2019-07-08 06:18:16.000000000","message":"Ah got it. That\u0027s what FPGA driver have done.  Is it better to clarify that RC is store in attribute tables not deployable. It\u0027s a little bit confusing :)","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"b20a8a90c1c589a0d8eead048c0f3e21fcec6120","unresolved":false,"context_lines":[{"line_number":274,"context_line":"* Do not publish PCI functions as resources in Nova. Instead, publish"},{"line_number":275,"context_line":"  RC/RP info to Nova, and keep RP-PCI mapping internally."},{"line_number":276,"context_line":""},{"line_number":277,"context_line":"* Cyborg should associate RPs/RCs and PFs/VFs with Deployables in its"},{"line_number":278,"context_line":"  internal DB."},{"line_number":279,"context_line":""},{"line_number":280,"context_line":"* Driver/agent interface needs to report device/region types so that"}],"source_content_type":"text/x-rst","patch_set":5,"id":"7faddb67_8bd92df4","line":277,"range":{"start_line":277,"start_character":15,"end_line":277,"end_character":62},"in_reply_to":"7faddb67_bbcff17d","updated":"2019-07-12 08:54:08.000000000","message":"Done","commit_id":"aea26bd26fcacc4a7714146015986527d6b19f8d"}]}