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{"/COMMIT_MSG":[{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"46ad10c46b7c102c07aa07db4a67104dd9c586bd","unresolved":false,"context_lines":[{"line_number":16,"context_line":""},{"line_number":17,"context_line":"In order to add the support for these specific accelerator, we propose to add"},{"line_number":18,"context_line":"a generic driver to manage these devices. We propose to add a new driver,"},{"line_number":19,"context_line":"\"AcceleratorDriver\", against exists FPGA, GPU driver."},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"Change-Id: I1efcb4e6bb51578c27b03dd8a800a5e289a94ff5"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"ffb9cba7_8714eba1","line":19,"updated":"2019-04-25 00:38:01.000000000","message":"This name is too general, because every driver is for some accelerator. We could call it a \u0027GenericDriver\u0027.\n\n\nWe already have a generic driver, as another comment says. Why not enhance that?\n\n\nWill the generic driver assume that the device supports SR-IOV? Or will it pass the PCI PF to the VM?\n\n\nThe spec should say what the generic device looks like.\n\n\nIs this meant to handle Ascend?","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"60cbbca9b260bedcfa8f49074bc5cb181f948361","unresolved":false,"context_lines":[{"line_number":16,"context_line":""},{"line_number":17,"context_line":"In order to add the support for these specific accelerator, we propose to add"},{"line_number":18,"context_line":"a generic driver to manage these devices. We propose to add a new driver,"},{"line_number":19,"context_line":"\"AcceleratorDriver\", against exists FPGA, GPU driver."},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"Change-Id: I1efcb4e6bb51578c27b03dd8a800a5e289a94ff5"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"ffb9cba7_901dea10","line":19,"in_reply_to":"ffb9cba7_8714eba1","updated":"2019-04-26 09:57:20.000000000","message":"Yes, it\u0027s for give a position for Ascend like device.\n\nSR-IOV or PCI PF maybe can become the capability which report in get_accelerator_stats ?","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"}],"specs/train/cyborg-accelerator-driver.rst":[{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"11c7acd71a8f0fd93f6080b96e7fec861d0751d2","unresolved":false,"context_lines":[{"line_number":8,"context_line":"Cyborg Accelerator Driver Proposal"},{"line_number":9,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"This spec propose to provide the initial desgin for Cyborg accelertor driver."},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"Problem description"},{"line_number":14,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":1,"id":"ffb9cba7_e52cdb48","line":11,"range":{"start_line":11,"start_character":10,"end_line":11,"end_character":17},"updated":"2019-04-24 07:57:35.000000000","message":"proposes","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"60cbbca9b260bedcfa8f49074bc5cb181f948361","unresolved":false,"context_lines":[{"line_number":8,"context_line":"Cyborg Accelerator Driver Proposal"},{"line_number":9,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"This spec propose to provide the initial desgin for Cyborg accelertor driver."},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"Problem description"},{"line_number":14,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":1,"id":"ffb9cba7_bb910a9c","line":11,"range":{"start_line":11,"start_character":10,"end_line":11,"end_character":17},"in_reply_to":"ffb9cba7_e52cdb48","updated":"2019-04-26 09:57:20.000000000","message":"Done","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"11c7acd71a8f0fd93f6080b96e7fec861d0751d2","unresolved":false,"context_lines":[{"line_number":23,"context_line":""},{"line_number":24,"context_line":"In order to add the support for these specific accelerator, we propose to add"},{"line_number":25,"context_line":"a generic driver to manage these devices. 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We hope the driver can provide the firmware"},{"line_number":33,"context_line":"  upgrade, device configure, device stats query."},{"line_number":34,"context_line":"- As a security accelerator vendor, I want add the driver in Cyborg with security"}],"source_content_type":"text/x-rst","patch_set":1,"id":"ffb9cba7_451b671a","line":31,"range":{"start_line":31,"start_character":65,"end_line":31,"end_character":71},"updated":"2019-04-24 07:57:35.000000000","message":"existing","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"60cbbca9b260bedcfa8f49074bc5cb181f948361","unresolved":false,"context_lines":[{"line_number":28,"context_line":"Use Cases"},{"line_number":29,"context_line":"---------"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"- As an AI chip vendor, I want add the driver in Cyborg, but the exists driver"},{"line_number":32,"context_line":"  type don\u0027t meet our requirement. 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Add a new base driver Named as \"AcceleratorDriver\""},{"line_number":40,"context_line":""},{"line_number":41,"context_line":"2. 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Add a new base driver Named as \"AcceleratorDriver\""},{"line_number":40,"context_line":""},{"line_number":41,"context_line":"2. As the initial version, the ``AcceleratorDriver`` should include the follow"},{"line_number":42,"context_line":"   interfaces:"}],"source_content_type":"text/x-rst","patch_set":1,"id":"ffb9cba7_a717afa3","line":39,"range":{"start_line":39,"start_character":3,"end_line":39,"end_character":53},"in_reply_to":"ffb9cba7_1b7e2f19","updated":"2019-04-25 00:38:01.000000000","message":"+1","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"60cbbca9b260bedcfa8f49074bc5cb181f948361","unresolved":false,"context_lines":[{"line_number":36,"context_line":""},{"line_number":37,"context_line":"Proposed change"},{"line_number":38,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":39,"context_line":"1. Add a new base driver Named as \"AcceleratorDriver\""},{"line_number":40,"context_line":""},{"line_number":41,"context_line":"2. As the initial version, the ``AcceleratorDriver`` should include the follow"},{"line_number":42,"context_line":"   interfaces:"}],"source_content_type":"text/x-rst","patch_set":1,"id":"ffb9cba7_10881a6f","line":39,"range":{"start_line":39,"start_character":3,"end_line":39,"end_character":53},"in_reply_to":"ffb9cba7_1b7e2f19","updated":"2019-04-26 09:57:20.000000000","message":"Done","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"46ad10c46b7c102c07aa07db4a67104dd9c586bd","unresolved":false,"context_lines":[{"line_number":44,"context_line":"   - discover()"},{"line_number":45,"context_line":"     Discover specific accelerator"},{"line_number":46,"context_line":""},{"line_number":47,"context_line":"   - deploy(device_path, image):"},{"line_number":48,"context_line":"     Upgrade or program the device with specific image."},{"line_number":49,"context_line":"     device_path: the sys path of accelerator device."},{"line_number":50,"context_line":"     image: The local path of programming image/firmware binary."}],"source_content_type":"text/x-rst","patch_set":1,"id":"ffb9cba7_470ef38d","line":47,"updated":"2019-04-25 00:38:01.000000000","message":"What is the device path? Is it a file system path like /sys/class/... , or a PCI PF?","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"11c7acd71a8f0fd93f6080b96e7fec861d0751d2","unresolved":false,"context_lines":[{"line_number":47,"context_line":"   - deploy(device_path, image):"},{"line_number":48,"context_line":"     Upgrade or program the device with specific image."},{"line_number":49,"context_line":"     device_path: the sys path of accelerator device."},{"line_number":50,"context_line":"     image: The local path of programming image/firmware binary."},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"   - get_accelerator_stats():"},{"line_number":53,"context_line":"     Collects accelerator stats. The ``get_accelerator_stats`` method is used"}],"source_content_type":"text/x-rst","patch_set":1,"id":"ffb9cba7_1ba38fa0","line":50,"range":{"start_line":50,"start_character":5,"end_line":50,"end_character":64},"updated":"2019-04-24 07:57:35.000000000","message":"we should consider cyborg/glance interaction here.  The image_uuid is also acceptable by this function in the future.","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":25738,"name":"Xinran WANG","email":"xin-ran.wang@intel.com","username":"Xinran"},"change_message_id":"11c7acd71a8f0fd93f6080b96e7fec861d0751d2","unresolved":false,"context_lines":[{"line_number":50,"context_line":"     image: The local path of programming image/firmware binary."},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"   - get_accelerator_stats():"},{"line_number":53,"context_line":"     Collects accelerator stats. The ``get_accelerator_stats`` method is used"},{"line_number":54,"context_line":"     to collect information from the accelerator about the accelerator"},{"line_number":55,"context_line":"     capabilities. Such as firmware version, performance info."},{"line_number":56,"context_line":""},{"line_number":57,"context_line":"After adding this ``AcceleratorDriver``, we could also make FPGA, GPU driver"},{"line_number":58,"context_line":"inherit from this driver, and make the driver interface"}],"source_content_type":"text/x-rst","patch_set":1,"id":"ffb9cba7_fbd55be6","line":55,"range":{"start_line":53,"start_character":4,"end_line":55,"end_character":18},"updated":"2019-04-24 07:57:35.000000000","message":"Where can we get accelerator stats, I think it varies with different devices. Should we store these information in cyborg DB. Will this be a part of traits which will report to placement?","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"60cbbca9b260bedcfa8f49074bc5cb181f948361","unresolved":false,"context_lines":[{"line_number":50,"context_line":"     image: The local path of programming image/firmware binary."},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"   - get_accelerator_stats():"},{"line_number":53,"context_line":"     Collects accelerator stats. The ``get_accelerator_stats`` method is used"},{"line_number":54,"context_line":"     to collect information from the accelerator about the accelerator"},{"line_number":55,"context_line":"     capabilities. Such as firmware version, performance info."},{"line_number":56,"context_line":""},{"line_number":57,"context_line":"After adding this ``AcceleratorDriver``, we could also make FPGA, GPU driver"},{"line_number":58,"context_line":"inherit from this driver, and make the driver interface"}],"source_content_type":"text/x-rst","patch_set":1,"id":"ffb9cba7_b0410e0e","line":55,"range":{"start_line":53,"start_character":4,"end_line":55,"end_character":18},"in_reply_to":"ffb9cba7_6711b7ac","updated":"2019-04-26 09:57:20.000000000","message":"Yes, so if it can be accessed from host, maybe we could just return something to show this device has been assigned?","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"46ad10c46b7c102c07aa07db4a67104dd9c586bd","unresolved":false,"context_lines":[{"line_number":50,"context_line":"     image: The local path of programming image/firmware binary."},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"   - get_accelerator_stats():"},{"line_number":53,"context_line":"     Collects accelerator stats. The ``get_accelerator_stats`` method is used"},{"line_number":54,"context_line":"     to collect information from the accelerator about the accelerator"},{"line_number":55,"context_line":"     capabilities. Such as firmware version, performance info."},{"line_number":56,"context_line":""},{"line_number":57,"context_line":"After adding this ``AcceleratorDriver``, we could also make FPGA, GPU driver"},{"line_number":58,"context_line":"inherit from this driver, and make the driver interface"}],"source_content_type":"text/x-rst","patch_set":1,"id":"ffb9cba7_6711b7ac","line":55,"range":{"start_line":53,"start_character":4,"end_line":55,"end_character":18},"in_reply_to":"ffb9cba7_fbd55be6","updated":"2019-04-25 00:38:01.000000000","message":"Once the PCI function is assigned to a VM, it cannot be accessed from the host, for Cyborg to get perf stats. For a SR-IOV device, the PF in the host may be used to get those stats, but it is not supported by all devices.","commit_id":"86aa89dc6c0d4a196906b17fb3a3c5ab1e0979df"},{"author":{"_account_id":7160,"name":"arkady kanevsky","email":"akanevsk@redhat.com","username":"arkady"},"change_message_id":"2401f01a4d4fd221b28640656f9bdf5c71098f64","unresolved":false,"context_lines":[{"line_number":8,"context_line":"Cyborg Accelerator Driver Proposal"},{"line_number":9,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"This spec proposes to provide the initial desgin for Cyborg accelertor driver."},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"Problem description"},{"line_number":14,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_72754998","line":11,"range":{"start_line":11,"start_character":42,"end_line":11,"end_character":48},"updated":"2019-05-02 22:23:20.000000000","message":"design","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"421b98c2cf541c506d2c0f429e585bd385d3431c","unresolved":false,"context_lines":[{"line_number":8,"context_line":"Cyborg Accelerator Driver Proposal"},{"line_number":9,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"This spec proposes to provide the initial desgin for Cyborg accelertor driver."},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"Problem description"},{"line_number":14,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_555b4f2d","line":11,"range":{"start_line":11,"start_character":42,"end_line":11,"end_character":48},"in_reply_to":"dfbec78f_72754998","updated":"2019-05-09 07:50:52.000000000","message":"Done","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":16,"context_line":"Currently, the FPGA and GPU have been supported in Cyborg, the capability to"},{"line_number":17,"context_line":"support the generic accelerator is not supported yet."},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"In general, these generic devices are the specific accelerator in some specific"},{"line_number":20,"context_line":"scenario. For example:"},{"line_number":21,"context_line":"1. The AI chips. which can be used for AI tarining and inference."},{"line_number":22,"context_line":"2. The security accelerator, which can be used for encryption and decryption."}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_10d22801","line":19,"range":{"start_line":19,"start_character":12,"end_line":19,"end_character":33},"updated":"2019-04-30 09:33:57.000000000","message":"It would be good to define what exactly a generic device means:\n* It is a PCI device, which may or may not support SR-IOV. It has a control path interface (PCI PF) and one or more attach handles (PCI VFs or, if there is no SR-IOV, the PF itself). It is attached to the VM via PCI functions (not mediated devices etc. -- though Cyborg can support them, that is not a generic device.)\n* It may need some device preparation as part of VM bringup (e.g. set some configuration data in the PF or the selected VF -- how we get that config data needs to be discussed).\n* It has some firmware or configuration that needs to be updated occasionally, but not as part of VM bringup or termination. That is done via the control path id (PCI PF).","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":18,"context_line":""},{"line_number":19,"context_line":"In general, these generic devices are the specific accelerator in some specific"},{"line_number":20,"context_line":"scenario. For example:"},{"line_number":21,"context_line":"1. The AI chips. which can be used for AI tarining and inference."},{"line_number":22,"context_line":"2. The security accelerator, which can be used for encryption and decryption."},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"In order to add the support for these specific accelerator, we propose to"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_30cf2c57","line":21,"range":{"start_line":21,"start_character":42,"end_line":21,"end_character":50},"updated":"2019-04-30 09:33:57.000000000","message":"training","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"421b98c2cf541c506d2c0f429e585bd385d3431c","unresolved":false,"context_lines":[{"line_number":18,"context_line":""},{"line_number":19,"context_line":"In general, these generic devices are the specific accelerator in some specific"},{"line_number":20,"context_line":"scenario. For example:"},{"line_number":21,"context_line":"1. The AI chips. which can be used for AI tarining and inference."},{"line_number":22,"context_line":"2. The security accelerator, which can be used for encryption and decryption."},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"In order to add the support for these specific accelerator, we propose to"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_f53fe3b2","line":21,"range":{"start_line":21,"start_character":42,"end_line":21,"end_character":50},"in_reply_to":"ffb9cba7_30cf2c57","updated":"2019-05-09 07:50:52.000000000","message":"Done","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":7160,"name":"arkady kanevsky","email":"akanevsk@redhat.com","username":"arkady"},"change_message_id":"2401f01a4d4fd221b28640656f9bdf5c71098f64","unresolved":false,"context_lines":[{"line_number":21,"context_line":"1. The AI chips. which can be used for AI tarining and inference."},{"line_number":22,"context_line":"2. The security accelerator, which can be used for encryption and decryption."},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"In order to add the support for these specific accelerator, we propose to"},{"line_number":25,"context_line":"improve the generic driver to manage these devices. We propose to improve the"},{"line_number":26,"context_line":"existing GenericDriver."},{"line_number":27,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_929f9db3","line":24,"range":{"start_line":24,"start_character":58,"end_line":24,"end_character":59},"updated":"2019-05-02 22:23:20.000000000","message":"s","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"421b98c2cf541c506d2c0f429e585bd385d3431c","unresolved":false,"context_lines":[{"line_number":21,"context_line":"1. The AI chips. which can be used for AI tarining and inference."},{"line_number":22,"context_line":"2. The security accelerator, which can be used for encryption and decryption."},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"In order to add the support for these specific accelerator, we propose to"},{"line_number":25,"context_line":"improve the generic driver to manage these devices. We propose to improve the"},{"line_number":26,"context_line":"existing GenericDriver."},{"line_number":27,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_153dd7ba","line":24,"range":{"start_line":24,"start_character":58,"end_line":24,"end_character":59},"in_reply_to":"dfbec78f_929f9db3","updated":"2019-05-09 07:50:52.000000000","message":"Done","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":22,"context_line":"2. The security accelerator, which can be used for encryption and decryption."},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"In order to add the support for these specific accelerator, we propose to"},{"line_number":25,"context_line":"improve the generic driver to manage these devices. We propose to improve the"},{"line_number":26,"context_line":"existing GenericDriver."},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"Use Cases"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_70b844e4","line":25,"range":{"start_line":25,"start_character":0,"end_line":25,"end_character":26},"updated":"2019-04-30 09:33:57.000000000","message":"+1. But maybe we should call this the GenericPCIDriver.","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"421b98c2cf541c506d2c0f429e585bd385d3431c","unresolved":false,"context_lines":[{"line_number":22,"context_line":"2. The security accelerator, which can be used for encryption and decryption."},{"line_number":23,"context_line":""},{"line_number":24,"context_line":"In order to add the support for these specific accelerator, we propose to"},{"line_number":25,"context_line":"improve the generic driver to manage these devices. We propose to improve the"},{"line_number":26,"context_line":"existing GenericDriver."},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"Use Cases"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_156637ef","line":25,"range":{"start_line":25,"start_character":0,"end_line":25,"end_character":26},"in_reply_to":"ffb9cba7_70b844e4","updated":"2019-05-09 07:50:52.000000000","message":"I think it\u0027s not a driver only for PCI address, it should be more generic, so I still prefer to make this driver as GenericDriver.","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":23,"context_line":""},{"line_number":24,"context_line":"In order to add the support for these specific accelerator, we propose to"},{"line_number":25,"context_line":"improve the generic driver to manage these devices. We propose to improve the"},{"line_number":26,"context_line":"existing GenericDriver."},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"Use Cases"},{"line_number":29,"context_line":"---------"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_d07d70b2","line":26,"updated":"2019-04-30 09:33:57.000000000","message":"The spec should clarify that, for every new device, we will introduce a new driver that inherits from the generic driver. The generic driver cannot be used as is, because the devices will differ in terms of vendor/device-model names, #accelerators/VFs etc.","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":28,"context_line":"Use Cases"},{"line_number":29,"context_line":"---------"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"- As an AI chip vendor, I want add the driver in Cyborg, but the existing driver"},{"line_number":32,"context_line":"  type don\u0027t meet our requirement. We hope the driver can provide the firmware"},{"line_number":33,"context_line":"  upgrade, device configure, device stats query."},{"line_number":34,"context_line":"- As a security accelerator vendor, I want add the driver in Cyborg with security"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_9007f882","line":31,"range":{"start_line":31,"start_character":26,"end_line":31,"end_character":34},"updated":"2019-04-30 09:33:57.000000000","message":"want to add","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"421b98c2cf541c506d2c0f429e585bd385d3431c","unresolved":false,"context_lines":[{"line_number":28,"context_line":"Use Cases"},{"line_number":29,"context_line":"---------"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"- As an AI chip vendor, I want add the driver in Cyborg, but the existing driver"},{"line_number":32,"context_line":"  type don\u0027t meet our requirement. We hope the driver can provide the firmware"},{"line_number":33,"context_line":"  upgrade, device configure, device stats query."},{"line_number":34,"context_line":"- As a security accelerator vendor, I want add the driver in Cyborg with security"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_f5960395","line":31,"range":{"start_line":31,"start_character":26,"end_line":31,"end_character":34},"in_reply_to":"ffb9cba7_9007f882","updated":"2019-05-09 07:50:52.000000000","message":"Done","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":29,"context_line":"---------"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"- As an AI chip vendor, I want add the driver in Cyborg, but the existing driver"},{"line_number":32,"context_line":"  type don\u0027t meet our requirement. We hope the driver can provide the firmware"},{"line_number":33,"context_line":"  upgrade, device configure, device stats query."},{"line_number":34,"context_line":"- As a security accelerator vendor, I want add the driver in Cyborg with security"},{"line_number":35,"context_line":"  accelerator configure and device stats query"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_b00c7ca5","line":32,"range":{"start_line":32,"start_character":7,"end_line":32,"end_character":12},"updated":"2019-04-30 09:33:57.000000000","message":"does not","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"421b98c2cf541c506d2c0f429e585bd385d3431c","unresolved":false,"context_lines":[{"line_number":29,"context_line":"---------"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"- As an AI chip vendor, I want add the driver in Cyborg, but the existing driver"},{"line_number":32,"context_line":"  type don\u0027t meet our requirement. We hope the driver can provide the firmware"},{"line_number":33,"context_line":"  upgrade, device configure, device stats query."},{"line_number":34,"context_line":"- As a security accelerator vendor, I want add the driver in Cyborg with security"},{"line_number":35,"context_line":"  accelerator configure and device stats query"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_1594f78a","line":32,"range":{"start_line":32,"start_character":7,"end_line":32,"end_character":12},"in_reply_to":"ffb9cba7_b00c7ca5","updated":"2019-05-09 07:50:52.000000000","message":"Done","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":7160,"name":"arkady kanevsky","email":"akanevsk@redhat.com","username":"arkady"},"change_message_id":"2401f01a4d4fd221b28640656f9bdf5c71098f64","unresolved":false,"context_lines":[{"line_number":36,"context_line":""},{"line_number":37,"context_line":"Proposed change"},{"line_number":38,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":39,"context_line":"As the initial version, the new ``GenericDriver`` should include the follow"},{"line_number":40,"context_line":"   interfaces:"},{"line_number":41,"context_line":""},{"line_number":42,"context_line":"   - discover()"},{"line_number":43,"context_line":"     Discover specific accelerator"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_d250b5d7","line":40,"range":{"start_line":39,"start_character":0,"end_line":40,"end_character":14},"updated":"2019-05-02 22:23:20.000000000","message":"Is the goal to create a generic class that each device will inherit from, irrespective what acceleration, specific capabilities device may provide?\n\nThese can include:\nDevice registration (with its unique , or will cyborg assign UUID to each device on registration?)\nDevice capabilities discovery,\ndevice life-cycle family of operations,\npower management of device(?)\ndevice monitoring APIs(?)","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"421b98c2cf541c506d2c0f429e585bd385d3431c","unresolved":false,"context_lines":[{"line_number":36,"context_line":""},{"line_number":37,"context_line":"Proposed change"},{"line_number":38,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":39,"context_line":"As the initial version, the new ``GenericDriver`` should include the follow"},{"line_number":40,"context_line":"   interfaces:"},{"line_number":41,"context_line":""},{"line_number":42,"context_line":"   - discover()"},{"line_number":43,"context_line":"     Discover specific accelerator"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_edb82177","line":40,"range":{"start_line":39,"start_character":0,"end_line":40,"end_character":14},"in_reply_to":"dfbec78f_d250b5d7","updated":"2019-05-09 07:50:52.000000000","message":"\u003e Device registration (with its unique , or will cyborg assign UUID to each device on registration?)\n\nYes, cyborg will register the device when discovering\n\n\u003e  Device capabilities discovery\n\nwill be covered in discovery interface\n\n\u003e device life-cycle family of operations,\n\nsure, list/get/update/show/show device\n\n\u003e power management of device(?)\n\nnot sure, maybe we need a configure/update/patch api for device?\n\n\u003e device monitoring APIs(?)\n\nit also will be covered in get_accelerator_stats","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":42,"context_line":"   - discover()"},{"line_number":43,"context_line":"     Discover specific accelerator"},{"line_number":44,"context_line":""},{"line_number":45,"context_line":"   - deploy(device_path, image):"},{"line_number":46,"context_line":"     Upgrade or program the device with specific image."},{"line_number":47,"context_line":"     device_path: the sys path of accelerator device."},{"line_number":48,"context_line":"     image: The local path of programming image/firmware binary, or the glance"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_306bac1e","line":45,"range":{"start_line":45,"start_character":25,"end_line":45,"end_character":30},"updated":"2019-04-30 09:33:57.000000000","message":"What data type is this? If it is a Glance UUID, the driver has to download from Glance itself. If the Cyborg agent has already downloaded it as a file, there are questions of security of that file and licensing. These are not specific to generic devices, but arise for FPGA programming too.","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":44,"context_line":""},{"line_number":45,"context_line":"   - deploy(device_path, image):"},{"line_number":46,"context_line":"     Upgrade or program the device with specific image."},{"line_number":47,"context_line":"     device_path: the sys path of accelerator device."},{"line_number":48,"context_line":"     image: The local path of programming image/firmware binary, or the glance"},{"line_number":49,"context_line":"     image uuid."},{"line_number":50,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_30f88c79","line":47,"range":{"start_line":47,"start_character":18,"end_line":47,"end_character":30},"updated":"2019-04-30 09:33:57.000000000","message":"You are assuming that each generic device will have a sys path interface. It will probably have a /sys/class/pci interface, but that is not a good interface to rely on across hypervisors. Instead, we should pass a control path id, which is hypervisor-dependent. For libvirt (kvm/xen), it is usually a PCI PF BDF.","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":51,"context_line":"   - get_accelerator_stats():"},{"line_number":52,"context_line":"     Collects accelerator stats. The ``get_accelerator_stats`` method is used"},{"line_number":53,"context_line":"     to collect information from the accelerator about the accelerator"},{"line_number":54,"context_line":"     capabilities. Such as firmware version, performance info."},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"After adding this ``AcceleratorDriver``, we could also make FPGA, GPU driver"},{"line_number":57,"context_line":"inherit from this driver, and make the driver interface"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_50e740ad","line":54,"range":{"start_line":54,"start_character":27,"end_line":54,"end_character":61},"updated":"2019-04-30 09:33:57.000000000","message":"These are 2 different categories. Firmware version changes rarely -- only on firmware update. So, it should be part of device discovery, not here. But the performance info needs to be collected every few minutes (or seconds?). How do we control the frequency of polling for performance info?\n\nSecondly, what performance stats do you collect? That will depend on the device and so it is not generic! I am not sure we can make this an OVO. We need to discuss.\n\nIt would be good to point out that performance stats should not be kept in Cyborg db. Generally, that requires some time-series db like Gnocchi, and is better handled by Telemetry/Ceilometer/Prometheus/...","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"421b98c2cf541c506d2c0f429e585bd385d3431c","unresolved":false,"context_lines":[{"line_number":51,"context_line":"   - get_accelerator_stats():"},{"line_number":52,"context_line":"     Collects accelerator stats. The ``get_accelerator_stats`` method is used"},{"line_number":53,"context_line":"     to collect information from the accelerator about the accelerator"},{"line_number":54,"context_line":"     capabilities. Such as firmware version, performance info."},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"After adding this ``AcceleratorDriver``, we could also make FPGA, GPU driver"},{"line_number":57,"context_line":"inherit from this driver, and make the driver interface"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_ad89c9ca","line":54,"range":{"start_line":54,"start_character":27,"end_line":54,"end_character":61},"in_reply_to":"ffb9cba7_50e740ad","updated":"2019-05-09 07:50:52.000000000","message":"Done","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":54,"context_line":"     capabilities. Such as firmware version, performance info."},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"After adding this ``AcceleratorDriver``, we could also make FPGA, GPU driver"},{"line_number":57,"context_line":"inherit from this driver, and make the driver interface"},{"line_number":58,"context_line":""},{"line_number":59,"context_line":"Alternatives"},{"line_number":60,"context_line":"------------"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_10054846","line":57,"range":{"start_line":57,"start_character":31,"end_line":57,"end_character":55},"updated":"2019-04-30 09:33:57.000000000","message":"Is this a complete sentence?","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"421b98c2cf541c506d2c0f429e585bd385d3431c","unresolved":false,"context_lines":[{"line_number":54,"context_line":"     capabilities. Such as firmware version, performance info."},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"After adding this ``AcceleratorDriver``, we could also make FPGA, GPU driver"},{"line_number":57,"context_line":"inherit from this driver, and make the driver interface"},{"line_number":58,"context_line":""},{"line_number":59,"context_line":"Alternatives"},{"line_number":60,"context_line":"------------"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_4d2fedf5","line":57,"range":{"start_line":57,"start_character":31,"end_line":57,"end_character":55},"in_reply_to":"ffb9cba7_10054846","updated":"2019-05-09 07:50:52.000000000","message":"Done","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":67,"context_line":""},{"line_number":68,"context_line":"REST API impact"},{"line_number":69,"context_line":"---------------"},{"line_number":70,"context_line":"None"},{"line_number":71,"context_line":""},{"line_number":72,"context_line":"Security impact"},{"line_number":73,"context_line":"---------------"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_f08c34d8","line":70,"range":{"start_line":70,"start_character":0,"end_line":70,"end_character":4},"updated":"2019-04-30 09:33:57.000000000","message":"Yes, but we probably need more content for the driver API.","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":91,"context_line":""},{"line_number":92,"context_line":"Developer impact"},{"line_number":93,"context_line":"----------------"},{"line_number":94,"context_line":"On the Cyborg Agent side, it relies on program() api implemented by vendor."},{"line_number":95,"context_line":""},{"line_number":96,"context_line":""},{"line_number":97,"context_line":"Implementation"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_909618f0","line":94,"range":{"start_line":94,"start_character":26,"end_line":94,"end_character":52},"updated":"2019-04-30 09:33:57.000000000","message":"It relies on the vendor for all APIs. :) Whether it is discover, performance counters, ...","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":104,"context_line":""},{"line_number":105,"context_line":"Work Items"},{"line_number":106,"context_line":"----------"},{"line_number":107,"context_line":"* Add a new driver for accelerator driver"},{"line_number":108,"context_line":""},{"line_number":109,"context_line":""},{"line_number":110,"context_line":"Dependencies"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_30b08c8a","line":107,"range":{"start_line":107,"start_character":2,"end_line":107,"end_character":41},"updated":"2019-04-30 09:33:57.000000000","message":"The term \u0027accelerator driver\u0027 is too generic, because FPGAs and GPUs are accelerators too. Also, you are not adding a new driver, but enhancing the generic driver, as you said.","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":7160,"name":"arkady kanevsky","email":"akanevsk@redhat.com","username":"arkady"},"change_message_id":"2401f01a4d4fd221b28640656f9bdf5c71098f64","unresolved":false,"context_lines":[{"line_number":120,"context_line":"References"},{"line_number":121,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":122,"context_line":"None"},{"line_number":123,"context_line":""},{"line_number":124,"context_line":"History"},{"line_number":125,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":126,"context_line":""},{"line_number":127,"context_line":".. list-table:: Revisions"}],"source_content_type":"text/x-rst","patch_set":2,"id":"dfbec78f_b253c1e2","line":124,"range":{"start_line":123,"start_character":0,"end_line":124,"end_character":7},"updated":"2019-05-02 22:23:20.000000000","message":"add a section for upgrade (of cyborg, rest of openstack)","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"96021ada63ef5985e646241a11ad3da0a305b9f6","unresolved":false,"context_lines":[{"line_number":129,"context_line":""},{"line_number":130,"context_line":"   * - Release Name"},{"line_number":131,"context_line":"     - Description"},{"line_number":132,"context_line":"   * - Rocky"},{"line_number":133,"context_line":"     - Introduced"}],"source_content_type":"text/x-rst","patch_set":2,"id":"ffb9cba7_5043c06c","line":132,"range":{"start_line":132,"start_character":7,"end_line":132,"end_character":12},"updated":"2019-04-30 09:33:57.000000000","message":"Train","commit_id":"be80cfc0e8d6e8ce92aef9cfd90b1e4fda84c83f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"8a32afc952f9ed6f86ff7355c18a51d8bf7b6bda","unresolved":false,"context_lines":[{"line_number":45,"context_line":"     Discover specific accelerator"},{"line_number":46,"context_line":"     output: raise NotImplementedError()"},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"   - update(control_path, image_id):"},{"line_number":49,"context_line":"     Upgrade the device firmware with specific image."},{"line_number":50,"context_line":"     control_path: the image update control path of device."},{"line_number":51,"context_line":"     image_id: The glance image id of the firmware binary. Although we perhaps"}],"source_content_type":"text/x-rst","patch_set":4,"id":"dfbec78f_2a92899f","line":48,"range":{"start_line":48,"start_character":26,"end_line":48,"end_character":34},"updated":"2019-05-10 02:23:34.000000000","message":"This should be changed into an image path. The agent should download the image file into some path in the file system and pass it to the driver, rather than require the driver to download it. The directory of download must be configurable in cyborg.conf. Also, if we don\u0027t use Glance, the driver need not know about it.\n\nThis downloaded file can be used for retries, i.e., if programing fails, we can retry the downloaded file. However, it should not be used as a cache, i.e., delete it after programming succeeds or certain #retries.","commit_id":"8aca0d30b99218106bd641e9306620b0b91efaf8"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"658bc541c433b7d6b900f785c540dba135f7544f","unresolved":false,"context_lines":[{"line_number":45,"context_line":"     Discover specific accelerator"},{"line_number":46,"context_line":"     output: raise NotImplementedError()"},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"   - update(control_path, image_id):"},{"line_number":49,"context_line":"     Upgrade the device firmware with specific image."},{"line_number":50,"context_line":"     control_path: the image update control path of device."},{"line_number":51,"context_line":"     image_id: The glance image id of the firmware binary. Although we perhaps"}],"source_content_type":"text/x-rst","patch_set":4,"id":"dfbec78f_a7cc6fbc","line":48,"range":{"start_line":48,"start_character":26,"end_line":48,"end_character":34},"in_reply_to":"dfbec78f_2a92899f","updated":"2019-05-10 08:16:18.000000000","message":"Done","commit_id":"8aca0d30b99218106bd641e9306620b0b91efaf8"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"8a32afc952f9ed6f86ff7355c18a51d8bf7b6bda","unresolved":false,"context_lines":[{"line_number":52,"context_line":"     have other potential image service"},{"line_number":53,"context_line":"     output: raise NotImplementedError()"},{"line_number":54,"context_line":""},{"line_number":55,"context_line":"   - get_accelerator_stats():"},{"line_number":56,"context_line":"     Collects accelerator stats. The ``get_accelerator_stats`` method is used"},{"line_number":57,"context_line":"     to collect information from the device about the device capabilities."},{"line_number":58,"context_line":"     Such as performance info like temprature, power, volt, packet_count info."}],"source_content_type":"text/x-rst","patch_set":4,"id":"dfbec78f_aaf3d909","line":55,"range":{"start_line":55,"start_character":5,"end_line":55,"end_character":26},"updated":"2019-05-10 02:23:34.000000000","message":"Can we change this to name to \u0027get_stats? Because it may include stats at different levels. Also, we should probably collect it for one device at a time?","commit_id":"8aca0d30b99218106bd641e9306620b0b91efaf8"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"658bc541c433b7d6b900f785c540dba135f7544f","unresolved":false,"context_lines":[{"line_number":52,"context_line":"     have other potential image service"},{"line_number":53,"context_line":"     output: raise NotImplementedError()"},{"line_number":54,"context_line":""},{"line_number":55,"context_line":"   - get_accelerator_stats():"},{"line_number":56,"context_line":"     Collects accelerator stats. The ``get_accelerator_stats`` method is used"},{"line_number":57,"context_line":"     to collect information from the device about the device capabilities."},{"line_number":58,"context_line":"     Such as performance info like temprature, power, volt, packet_count info."}],"source_content_type":"text/x-rst","patch_set":4,"id":"dfbec78f_c7cf23ae","line":55,"range":{"start_line":55,"start_character":5,"end_line":55,"end_character":26},"in_reply_to":"dfbec78f_aaf3d909","updated":"2019-05-10 08:16:18.000000000","message":"Done","commit_id":"8aca0d30b99218106bd641e9306620b0b91efaf8"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"0a083a27afafdd7af7388c49c99787a72a931bcf","unresolved":false,"context_lines":[{"line_number":65,"context_line":"inherits from this ``GenericDriver``."},{"line_number":66,"context_line":""},{"line_number":67,"context_line":""},{"line_number":68,"context_line":"2. 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The region type id may not"},{"line_number":78,"context_line":"     be needed unless there are multiple regions in the same device."},{"line_number":79,"context_line":""}],"source_content_type":"text/x-rst","patch_set":4,"id":"dfbec78f_8ad8557f","line":76,"range":{"start_line":76,"start_character":5,"end_line":76,"end_character":59},"updated":"2019-05-10 02:23:34.000000000","message":"Please match the method signature in Line 58 of https://review.opendev.org/#/c/626057/9/cyborg/accelerator/drivers/fpga/intel/driver.py","commit_id":"8aca0d30b99218106bd641e9306620b0b91efaf8"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"658bc541c433b7d6b900f785c540dba135f7544f","unresolved":false,"context_lines":[{"line_number":73,"context_line":"The ``discover``, ``update``, ``get_accelerator_stats`` should be implemented"},{"line_number":74,"context_line":"in the FPGA driver. and the below interface is the FPGA specifc interface:"},{"line_number":75,"context_line":""},{"line_number":76,"context_line":"   - program(device_id, bitstream_buf, region_type_id\u003dNone)"},{"line_number":77,"context_line":"     Programs the bitstream in the given buffer. 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Existing existing driver change"},{"line_number":69,"context_line":"We should also improve FPGA, GPU driver to inherit from this driver and"},{"line_number":70,"context_line":"implements the base driver interface."},{"line_number":71,"context_line":""},{"line_number":72,"context_line":"* The generic FPGA driver interface:"}],"source_content_type":"text/x-rst","patch_set":5,"id":"bfb3d3c7_45babdde","line":69,"range":{"start_line":69,"start_character":27,"end_line":69,"end_character":29},"updated":"2019-05-17 08:31:24.000000000","message":"and","commit_id":"ff6472a5b864be2ba98a87bd2e8ec05a3d4eed65"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"00a2e3871b92c5c9c71cb5aa0e1382786fb9fcdf","unresolved":false,"context_lines":[{"line_number":66,"context_line":""},{"line_number":67,"context_line":""},{"line_number":68,"context_line":"2. Existing existing driver change"},{"line_number":69,"context_line":"We should also improve FPGA, GPU driver to inherit from this driver and"},{"line_number":70,"context_line":"implements the base driver interface."},{"line_number":71,"context_line":""},{"line_number":72,"context_line":"* The generic FPGA driver interface:"}],"source_content_type":"text/x-rst","patch_set":5,"id":"bfb3d3c7_449b8a71","line":69,"range":{"start_line":69,"start_character":27,"end_line":69,"end_character":29},"in_reply_to":"bfb3d3c7_45babdde","updated":"2019-05-21 11:04:04.000000000","message":"Done","commit_id":"ff6472a5b864be2ba98a87bd2e8ec05a3d4eed65"},{"author":{"_account_id":22899,"name":"coco-Gao","email":"419546439@qq.com","username":"Coco"},"change_message_id":"8e3cc44e0d7410ded0910125d41cec29fdda16f0","unresolved":false,"context_lines":[{"line_number":39,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":40,"context_line":"1. The Generic driver change"},{"line_number":41,"context_line":"As the initial version, the new ``GenericDriver`` should include the following"},{"line_number":42,"context_line":"attributes:"},{"line_number":43,"context_line":""},{"line_number":44,"context_line":"   - VENDOR: the vendor name of the driver."},{"line_number":45,"context_line":"   - TYPE: the type of the driver, such as, \"FPGA\", \"GPU\""}],"source_content_type":"text/x-rst","patch_set":7,"id":"bfb3d3c7_13a072f4","line":42,"range":{"start_line":42,"start_character":0,"end_line":42,"end_character":10},"updated":"2019-05-20 09:41:45.000000000","message":"About the must-have attributes pls refer to the devices table\u0027s fields which are setted: nullable\u003dFalse. Or you can refer to GPUDriver.","commit_id":"767d914dece89e1f234865309beb931fef50a0af"},{"author":{"_account_id":17813,"name":"wangzhh","email":"wzh_1993@126.com","username":"wangzhh"},"change_message_id":"e2745eccac9c90a5b0b34b32170bf22665c1c0c8","unresolved":false,"context_lines":[{"line_number":39,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":40,"context_line":"1. The Generic driver change"},{"line_number":41,"context_line":"As the initial version, the new ``GenericDriver`` should include the following"},{"line_number":42,"context_line":"attributes:"},{"line_number":43,"context_line":""},{"line_number":44,"context_line":"   - VENDOR: the vendor name of the driver."},{"line_number":45,"context_line":"   - TYPE: the type of the driver, such as, \"FPGA\", \"GPU\""}],"source_content_type":"text/x-rst","patch_set":7,"id":"bfb3d3c7_d99d1b5a","line":42,"range":{"start_line":42,"start_character":0,"end_line":42,"end_character":10},"in_reply_to":"bfb3d3c7_13a072f4","updated":"2019-05-20 11:54:41.000000000","message":"These attributes are not the driver ovo attributes, so we don\u0027t need to refer to the device table.","commit_id":"767d914dece89e1f234865309beb931fef50a0af"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"00a2e3871b92c5c9c71cb5aa0e1382786fb9fcdf","unresolved":false,"context_lines":[{"line_number":39,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":40,"context_line":"1. The Generic driver change"},{"line_number":41,"context_line":"As the initial version, the new ``GenericDriver`` should include the following"},{"line_number":42,"context_line":"attributes:"},{"line_number":43,"context_line":""},{"line_number":44,"context_line":"   - VENDOR: the vendor name of the driver."},{"line_number":45,"context_line":"   - TYPE: the type of the driver, such as, \"FPGA\", \"GPU\""}],"source_content_type":"text/x-rst","patch_set":7,"id":"bfb3d3c7_0cd35e3a","line":42,"range":{"start_line":42,"start_character":0,"end_line":42,"end_character":10},"in_reply_to":"bfb3d3c7_d99d1b5a","updated":"2019-05-21 11:04:04.000000000","message":"@coco Agree with wangzhh, current we only need VENDOR/TYPE to distinct the different driver.","commit_id":"767d914dece89e1f234865309beb931fef50a0af"},{"author":{"_account_id":17813,"name":"wangzhh","email":"wzh_1993@126.com","username":"wangzhh"},"change_message_id":"e2745eccac9c90a5b0b34b32170bf22665c1c0c8","unresolved":false,"context_lines":[{"line_number":44,"context_line":"   - VENDOR: the vendor name of the driver."},{"line_number":45,"context_line":"   - TYPE: the type of the driver, such as, \"FPGA\", \"GPU\""},{"line_number":46,"context_line":""},{"line_number":47,"context_line":"and the following interfaces also should be included:"},{"line_number":48,"context_line":""},{"line_number":49,"context_line":"   - discover()"},{"line_number":50,"context_line":"     Discover specific accelerator"}],"source_content_type":"text/x-rst","patch_set":7,"id":"bfb3d3c7_f9dc9f19","line":47,"updated":"2019-05-20 11:54:41.000000000","message":"Should we define the create or init function of a driver here? I\u0027m not clear your design about it.","commit_id":"767d914dece89e1f234865309beb931fef50a0af"},{"author":{"_account_id":17813,"name":"wangzhh","email":"wzh_1993@126.com","username":"wangzhh"},"change_message_id":"9996e6df68cbf4cdefc6c2557629ed55c23989e4","unresolved":false,"context_lines":[{"line_number":44,"context_line":"   - VENDOR: the vendor name of the driver."},{"line_number":45,"context_line":"   - TYPE: the type of the driver, such as, \"FPGA\", \"GPU\""},{"line_number":46,"context_line":""},{"line_number":47,"context_line":"and the following interfaces also should be included:"},{"line_number":48,"context_line":""},{"line_number":49,"context_line":"   - discover()"},{"line_number":50,"context_line":"     Discover specific accelerator"}],"source_content_type":"text/x-rst","patch_set":7,"id":"bfb3d3c7_4604c34a","line":47,"in_reply_to":"bfb3d3c7_8cf8aec4","updated":"2019-05-22 01:23:49.000000000","message":"OK, just split the difference, we can merge it first and then improve it.","commit_id":"767d914dece89e1f234865309beb931fef50a0af"},{"author":{"_account_id":20722,"name":"Yikun Jiang","email":"yikunkero@gmail.com","username":"yikunkero"},"change_message_id":"00a2e3871b92c5c9c71cb5aa0e1382786fb9fcdf","unresolved":false,"context_lines":[{"line_number":44,"context_line":"   - VENDOR: the vendor name of the driver."},{"line_number":45,"context_line":"   - TYPE: the type of the driver, such as, \"FPGA\", \"GPU\""},{"line_number":46,"context_line":""},{"line_number":47,"context_line":"and the following interfaces also should be included:"},{"line_number":48,"context_line":""},{"line_number":49,"context_line":"   - discover()"},{"line_number":50,"context_line":"     Discover specific accelerator"}],"source_content_type":"text/x-rst","patch_set":7,"id":"bfb3d3c7_8cf8aec4","line":47,"in_reply_to":"bfb3d3c7_f9dc9f19","updated":"2019-05-21 11:04:04.000000000","message":"I think we had an agreement in PTG, we can add these interfaces at first, and then add other interfaces later.\n\nSo I think these interfaces are enough for npu/gpu/fpga.","commit_id":"767d914dece89e1f234865309beb931fef50a0af"}]}