)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":26458,"name":"Brin Zhang","email":"zhangbailin@inspur.com","username":"zhangbailin"},"change_message_id":"03063d20f3b3814122ab956e4587ed61fc133ef6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"ec5c1bbb_28a89ed1","updated":"2021-10-20 08:50:18.000000000","message":"this is should be update, as this talked on PTG https://etherpad.opendev.org/p/cyborg-yoga-ptg#54","commit_id":"78bda6ae84e064d5bf77adc661bcbdc27cf069d5"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"05b3bd3af6abe680a4148830767220f0d235806c","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"b66f395a_14ddbf61","in_reply_to":"ec5c1bbb_28a89ed1","updated":"2021-10-28 08:20:30.000000000","message":"Done","commit_id":"78bda6ae84e064d5bf77adc661bcbdc27cf069d5"},{"author":{"_account_id":26458,"name":"Brin Zhang","email":"zhangbailin@inspur.com","username":"zhangbailin"},"change_message_id":"4b5b115958909ac3780a8b42542b4a7602437160","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":10,"id":"08db74df_85aa25f4","updated":"2021-11-09 08:35:18.000000000","message":"LGTM","commit_id":"3daa899968cb6da69723c0005befb1a01cd8394c"}],"specs/yoga/approved/add-xilinx-fpga-driver.rst":[{"author":{"_account_id":26458,"name":"Brin Zhang","email":"zhangbailin@inspur.com","username":"zhangbailin"},"change_message_id":"dfc0631e5dc572afba257d41f7a5d76cd6d835d1","unresolved":true,"context_lines":[{"line_number":16,"context_line":"Problem description"},{"line_number":17,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"This spec will add an Xilinx FPGA driver for Cyborg to manage specific"},{"line_number":20,"context_line":"Xilinx FPGA devices."},{"line_number":21,"context_line":""},{"line_number":22,"context_line":"Use Cases"},{"line_number":23,"context_line":"---------"}],"source_content_type":"text/x-rst","patch_set":4,"id":"6434a27d_31c78312","line":20,"range":{"start_line":19,"start_character":0,"end_line":20,"end_character":20},"updated":"2021-08-15 07:28:19.000000000","message":"IMO, this seems not like an issue description, may you can say: \"We want to use Cyborg manage the Xilinx FPGA devices, but there is not driver for it, and we want to add the Xilinx FPGA driver to support managing Xilinx FPGA devices by Cyborg.\"","commit_id":"6fa4f6fdf9c2073f39d3c11ae8e1907c973f3e8a"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"bd776a1d25cf5610b52e9dd2754475725aa3f927","unresolved":false,"context_lines":[{"line_number":16,"context_line":"Problem description"},{"line_number":17,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"This spec will add an Xilinx FPGA driver for Cyborg to manage specific"},{"line_number":20,"context_line":"Xilinx FPGA devices."},{"line_number":21,"context_line":""},{"line_number":22,"context_line":"Use Cases"},{"line_number":23,"context_line":"---------"}],"source_content_type":"text/x-rst","patch_set":4,"id":"951e382a_16ea3df9","line":20,"range":{"start_line":19,"start_character":0,"end_line":20,"end_character":20},"in_reply_to":"6434a27d_31c78312","updated":"2021-08-17 10:26:42.000000000","message":"Done","commit_id":"6fa4f6fdf9c2073f39d3c11ae8e1907c973f3e8a"},{"author":{"_account_id":26458,"name":"Brin Zhang","email":"zhangbailin@inspur.com","username":"zhangbailin"},"change_message_id":"dfc0631e5dc572afba257d41f7a5d76cd6d835d1","unresolved":true,"context_lines":[{"line_number":70,"context_line":""},{"line_number":71,"context_line":"Data model impact"},{"line_number":72,"context_line":"-----------------"},{"line_number":73,"context_line":""},{"line_number":74,"context_line":"Xilinx FPGA driver will not touch Data model."},{"line_number":75,"context_line":"The Cyborg Agent can call Xilinx FPGA driver to update the database"},{"line_number":76,"context_line":"during the discover operation."}],"source_content_type":"text/x-rst","patch_set":4,"id":"680e3f5b_02517f38","line":73,"updated":"2021-08-15 07:28:19.000000000","message":"\"None\"\nBelow is your instruction to make the reader clearly.","commit_id":"6fa4f6fdf9c2073f39d3c11ae8e1907c973f3e8a"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"bd776a1d25cf5610b52e9dd2754475725aa3f927","unresolved":false,"context_lines":[{"line_number":70,"context_line":""},{"line_number":71,"context_line":"Data model impact"},{"line_number":72,"context_line":"-----------------"},{"line_number":73,"context_line":""},{"line_number":74,"context_line":"Xilinx FPGA driver will not touch Data model."},{"line_number":75,"context_line":"The Cyborg Agent can call Xilinx FPGA driver to update the database"},{"line_number":76,"context_line":"during the discover operation."}],"source_content_type":"text/x-rst","patch_set":4,"id":"0de876cf_2ad74962","line":73,"in_reply_to":"680e3f5b_02517f38","updated":"2021-08-17 10:26:42.000000000","message":"Done","commit_id":"6fa4f6fdf9c2073f39d3c11ae8e1907c973f3e8a"},{"author":{"_account_id":26458,"name":"Brin Zhang","email":"zhangbailin@inspur.com","username":"zhangbailin"},"change_message_id":"dfc0631e5dc572afba257d41f7a5d76cd6d835d1","unresolved":true,"context_lines":[{"line_number":93,"context_line":"Other end user impact"},{"line_number":94,"context_line":"---------------------"},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"User can manage Xilinx FPGA by Cyborg Xilinx FPGA driver. Such as list"},{"line_number":97,"context_line":"of the Xilinx FPGA devices, report the details of all available Xilinx"},{"line_number":98,"context_line":"FPGA accelerators on the host, binding with Xilinx FPGA and so on."},{"line_number":99,"context_line":""}],"source_content_type":"text/x-rst","patch_set":4,"id":"e1055979_0867afe9","line":96,"range":{"start_line":96,"start_character":31,"end_line":96,"end_character":38},"updated":"2021-08-15 07:28:19.000000000","message":"redundant","commit_id":"6fa4f6fdf9c2073f39d3c11ae8e1907c973f3e8a"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"bd776a1d25cf5610b52e9dd2754475725aa3f927","unresolved":false,"context_lines":[{"line_number":93,"context_line":"Other end user impact"},{"line_number":94,"context_line":"---------------------"},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"User can manage Xilinx FPGA by Cyborg Xilinx FPGA driver. Such as list"},{"line_number":97,"context_line":"of the Xilinx FPGA devices, report the details of all available Xilinx"},{"line_number":98,"context_line":"FPGA accelerators on the host, binding with Xilinx FPGA and so on."},{"line_number":99,"context_line":""}],"source_content_type":"text/x-rst","patch_set":4,"id":"80698d25_c5bf055a","line":96,"range":{"start_line":96,"start_character":31,"end_line":96,"end_character":38},"in_reply_to":"e1055979_0867afe9","updated":"2021-08-17 10:26:42.000000000","message":"Done","commit_id":"6fa4f6fdf9c2073f39d3c11ae8e1907c973f3e8a"},{"author":{"_account_id":26458,"name":"Brin Zhang","email":"zhangbailin@inspur.com","username":"zhangbailin"},"change_message_id":"dfc0631e5dc572afba257d41f7a5d76cd6d835d1","unresolved":true,"context_lines":[{"line_number":142,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":143,"context_line":""},{"line_number":144,"context_line":"Document Xilinx FPGA driver in Cyborg project."},{"line_number":145,"context_line":"Test report in Cyborg wiki"},{"line_number":146,"context_line":""},{"line_number":147,"context_line":"References"},{"line_number":148,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":4,"id":"cfdc6b51_7af55173","line":145,"range":{"start_line":145,"start_character":0,"end_line":145,"end_character":26},"updated":"2021-08-15 07:28:19.000000000","message":"+1, Good point.","commit_id":"6fa4f6fdf9c2073f39d3c11ae8e1907c973f3e8a"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"bd776a1d25cf5610b52e9dd2754475725aa3f927","unresolved":false,"context_lines":[{"line_number":142,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":143,"context_line":""},{"line_number":144,"context_line":"Document Xilinx FPGA driver in Cyborg project."},{"line_number":145,"context_line":"Test report in Cyborg wiki"},{"line_number":146,"context_line":""},{"line_number":147,"context_line":"References"},{"line_number":148,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":4,"id":"b143e650_6932e60d","line":145,"range":{"start_line":145,"start_character":0,"end_line":145,"end_character":26},"in_reply_to":"cfdc6b51_7af55173","updated":"2021-08-17 10:26:42.000000000","message":"Done","commit_id":"6fa4f6fdf9c2073f39d3c11ae8e1907c973f3e8a"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"b00fb1ea3e61d21d3edee04f32c76eb3c47a40ef","unresolved":true,"context_lines":[{"line_number":48,"context_line":"- ``discover()``: This function works by executing ``lspci`` command"},{"line_number":49,"context_line":"  and reports devices\u0027 raw info sample as following::"},{"line_number":50,"context_line":""},{"line_number":51,"context_line":"    ["},{"line_number":52,"context_line":"      {"},{"line_number":53,"context_line":"      \"vendor\": \"10ee\","},{"line_number":54,"context_line":"      \"product\": \"5000\","},{"line_number":55,"context_line":"      \"device\": \"0000:3b:00.0\""},{"line_number":56,"context_line":"      },"},{"line_number":57,"context_line":"      {"},{"line_number":58,"context_line":"      \"vendor\": \"10ee\","},{"line_number":59,"context_line":"      \"product\": \"5001\","},{"line_number":60,"context_line":"      \"device\": \"0000:3b:00.1\""},{"line_number":61,"context_line":"      }"},{"line_number":62,"context_line":"    ]"},{"line_number":63,"context_line":""},{"line_number":64,"context_line":"  In above example, \"5000\" is the MGMT PF and \"5001\" is the USER PF. In"},{"line_number":65,"context_line":"  general, only USER PF device can be pass-through to vm. So the driver should"}],"source_content_type":"text/x-rst","patch_set":6,"id":"4f10da32_713765c7","line":62,"range":{"start_line":51,"start_character":0,"end_line":62,"end_character":5},"updated":"2021-10-20 01:42:11.000000000","message":"only need to report MGMT PF info, but bind MAMT and USER PF when create FPGA vm.","commit_id":"78bda6ae84e064d5bf77adc661bcbdc27cf069d5"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"05b3bd3af6abe680a4148830767220f0d235806c","unresolved":false,"context_lines":[{"line_number":48,"context_line":"- ``discover()``: This function works by executing ``lspci`` command"},{"line_number":49,"context_line":"  and reports devices\u0027 raw info sample as following::"},{"line_number":50,"context_line":""},{"line_number":51,"context_line":"    ["},{"line_number":52,"context_line":"      {"},{"line_number":53,"context_line":"      \"vendor\": \"10ee\","},{"line_number":54,"context_line":"      \"product\": \"5000\","},{"line_number":55,"context_line":"      \"device\": \"0000:3b:00.0\""},{"line_number":56,"context_line":"      },"},{"line_number":57,"context_line":"      {"},{"line_number":58,"context_line":"      \"vendor\": \"10ee\","},{"line_number":59,"context_line":"      \"product\": \"5001\","},{"line_number":60,"context_line":"      \"device\": \"0000:3b:00.1\""},{"line_number":61,"context_line":"      }"},{"line_number":62,"context_line":"    ]"},{"line_number":63,"context_line":""},{"line_number":64,"context_line":"  In above example, \"5000\" is the MGMT PF and \"5001\" is the USER PF. In"},{"line_number":65,"context_line":"  general, only USER PF device can be pass-through to vm. So the driver should"}],"source_content_type":"text/x-rst","patch_set":6,"id":"17ecd954_82ba67a0","line":62,"range":{"start_line":51,"start_character":0,"end_line":62,"end_character":5},"in_reply_to":"4f10da32_713765c7","updated":"2021-10-28 08:20:30.000000000","message":"Done","commit_id":"78bda6ae84e064d5bf77adc661bcbdc27cf069d5"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"b00fb1ea3e61d21d3edee04f32c76eb3c47a40ef","unresolved":true,"context_lines":[{"line_number":68,"context_line":"  Also the driver should create records in deployable table only for USER PF"},{"line_number":69,"context_line":"  devices."},{"line_number":70,"context_line":""},{"line_number":71,"context_line":"- ``program()``: This function works by executing ``xbmgmt program`` command"},{"line_number":72,"context_line":"  which is included with the XRT installation package.[2]_"},{"line_number":73,"context_line":""},{"line_number":74,"context_line":"Below is the objects to describe a FPGA device which"}],"source_content_type":"text/x-rst","patch_set":6,"id":"629f6a3b_05371258","line":71,"range":{"start_line":71,"start_character":4,"end_line":71,"end_character":11},"updated":"2021-10-20 01:42:11.000000000","message":"program when boot a vm by MGMT PF and used by USER PF when the vm is created?","commit_id":"78bda6ae84e064d5bf77adc661bcbdc27cf069d5"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"05b3bd3af6abe680a4148830767220f0d235806c","unresolved":false,"context_lines":[{"line_number":68,"context_line":"  Also the driver should create records in deployable table only for USER PF"},{"line_number":69,"context_line":"  devices."},{"line_number":70,"context_line":""},{"line_number":71,"context_line":"- ``program()``: This function works by executing ``xbmgmt program`` command"},{"line_number":72,"context_line":"  which is included with the XRT installation package.[2]_"},{"line_number":73,"context_line":""},{"line_number":74,"context_line":"Below is the objects to describe a FPGA device which"}],"source_content_type":"text/x-rst","patch_set":6,"id":"e20cb274_51cf7851","line":71,"range":{"start_line":71,"start_character":4,"end_line":71,"end_character":11},"in_reply_to":"629f6a3b_05371258","updated":"2021-10-28 08:20:30.000000000","message":"Done","commit_id":"78bda6ae84e064d5bf77adc661bcbdc27cf069d5"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"b00fb1ea3e61d21d3edee04f32c76eb3c47a40ef","unresolved":true,"context_lines":[{"line_number":78,"context_line":""},{"line_number":79,"context_line":"  Hardware     Driver objects       Placement data model"},{"line_number":80,"context_line":"     |               |                      |"},{"line_number":81,"context_line":"  1 FPGA         2 devices                  |"},{"line_number":82,"context_line":"     |               |                      |"},{"line_number":83,"context_line":"     |         1 deployable       ---\u003e resource_provider"},{"line_number":84,"context_line":"     |               |            ---\u003e parent resource_provider: compute node"}],"source_content_type":"text/x-rst","patch_set":6,"id":"5315f242_d4ec71ae","line":81,"range":{"start_line":81,"start_character":17,"end_line":81,"end_character":19},"updated":"2021-10-20 01:42:11.000000000","message":"1 devices","commit_id":"78bda6ae84e064d5bf77adc661bcbdc27cf069d5"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"05b3bd3af6abe680a4148830767220f0d235806c","unresolved":false,"context_lines":[{"line_number":78,"context_line":""},{"line_number":79,"context_line":"  Hardware     Driver objects       Placement data model"},{"line_number":80,"context_line":"     |               |                      |"},{"line_number":81,"context_line":"  1 FPGA         2 devices                  |"},{"line_number":82,"context_line":"     |               |                      |"},{"line_number":83,"context_line":"     |         1 deployable       ---\u003e resource_provider"},{"line_number":84,"context_line":"     |               |            ---\u003e parent resource_provider: compute node"}],"source_content_type":"text/x-rst","patch_set":6,"id":"d4c86ccc_ff87c073","line":81,"range":{"start_line":81,"start_character":17,"end_line":81,"end_character":19},"in_reply_to":"5315f242_d4ec71ae","updated":"2021-10-28 08:20:30.000000000","message":"Done","commit_id":"78bda6ae84e064d5bf77adc661bcbdc27cf069d5"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"b00fb1ea3e61d21d3edee04f32c76eb3c47a40ef","unresolved":true,"context_lines":[{"line_number":128,"context_line":"Other deployer impact"},{"line_number":129,"context_line":"---------------------"},{"line_number":130,"context_line":""},{"line_number":131,"context_line":"None"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"Developer impact"},{"line_number":134,"context_line":"----------------"}],"source_content_type":"text/x-rst","patch_set":6,"id":"1b2a9fc2_e8e3f3a3","line":131,"range":{"start_line":131,"start_character":0,"end_line":131,"end_character":4},"updated":"2021-10-20 01:42:11.000000000","message":"add driver configuration.","commit_id":"78bda6ae84e064d5bf77adc661bcbdc27cf069d5"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"05b3bd3af6abe680a4148830767220f0d235806c","unresolved":false,"context_lines":[{"line_number":128,"context_line":"Other deployer impact"},{"line_number":129,"context_line":"---------------------"},{"line_number":130,"context_line":""},{"line_number":131,"context_line":"None"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"Developer impact"},{"line_number":134,"context_line":"----------------"}],"source_content_type":"text/x-rst","patch_set":6,"id":"1df56a27_4a3616b5","line":131,"range":{"start_line":131,"start_character":0,"end_line":131,"end_character":4},"in_reply_to":"1b2a9fc2_e8e3f3a3","updated":"2021-10-28 08:20:30.000000000","message":"Done","commit_id":"78bda6ae84e064d5bf77adc661bcbdc27cf069d5"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"58bf8dd8c023aea73e42866344b5cfe3b2ffc635","unresolved":true,"context_lines":[{"line_number":31,"context_line":""},{"line_number":32,"context_line":"* As a user, I would like to boot up a VM with Xilinx FPGA device."},{"line_number":33,"context_line":"  Cyborg should be able to manage this kind of acceleration resources,"},{"line_number":34,"context_line":"  assign it to the VM(binding) and programming it."},{"line_number":35,"context_line":""},{"line_number":36,"context_line":"Proposed changes"},{"line_number":37,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":9,"id":"46b1a21d_ad5879c2","line":34,"range":{"start_line":34,"start_character":35,"end_line":34,"end_character":49},"updated":"2021-10-29 07:52:17.000000000","message":"programming is not support now, right?","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"5483de4e5d06122c726435403c7dac434efc4310","unresolved":true,"context_lines":[{"line_number":31,"context_line":""},{"line_number":32,"context_line":"* As a user, I would like to boot up a VM with Xilinx FPGA device."},{"line_number":33,"context_line":"  Cyborg should be able to manage this kind of acceleration resources,"},{"line_number":34,"context_line":"  assign it to the VM(binding) and programming it."},{"line_number":35,"context_line":""},{"line_number":36,"context_line":"Proposed changes"},{"line_number":37,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":9,"id":"a16f048f_1ffb9c0e","line":34,"range":{"start_line":34,"start_character":35,"end_line":34,"end_character":49},"in_reply_to":"46b1a21d_ad5879c2","updated":"2021-11-01 07:32:32.000000000","message":"Add `program()` method to supporting pre-program before binding it to vm.","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"58bf8dd8c023aea73e42866344b5cfe3b2ffc635","unresolved":true,"context_lines":[{"line_number":65,"context_line":""},{"line_number":66,"context_line":"  In above example, \"5000\" is the mgmt PF. So the driver should"},{"line_number":67,"context_line":"  add three traits for one device, including \"CUSTOM_FPGA_\u003cVENDOR_ID\u003e\","},{"line_number":68,"context_line":"  \"CUSTOM_FPGA_PRODUCT_ID_\u003cID\u003e\", and \"CUSTOM_FPGA_XILINX_PF_\u003cMGMT\u003e\"."},{"line_number":69,"context_line":"  Also the driver should create records in deployable table only for the"},{"line_number":70,"context_line":"  device. For now, only when both mgmt PF and user PF are binded to one vm,"},{"line_number":71,"context_line":"  and end user can program the FPGA device."}],"source_content_type":"text/x-rst","patch_set":9,"id":"1dc79223_5d4b6f7e","line":68,"range":{"start_line":68,"start_character":38,"end_line":68,"end_character":66},"updated":"2021-10-29 07:52:17.000000000","message":"will we need report this trait?","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"5483de4e5d06122c726435403c7dac434efc4310","unresolved":false,"context_lines":[{"line_number":65,"context_line":""},{"line_number":66,"context_line":"  In above example, \"5000\" is the mgmt PF. So the driver should"},{"line_number":67,"context_line":"  add three traits for one device, including \"CUSTOM_FPGA_\u003cVENDOR_ID\u003e\","},{"line_number":68,"context_line":"  \"CUSTOM_FPGA_PRODUCT_ID_\u003cID\u003e\", and \"CUSTOM_FPGA_XILINX_PF_\u003cMGMT\u003e\"."},{"line_number":69,"context_line":"  Also the driver should create records in deployable table only for the"},{"line_number":70,"context_line":"  device. For now, only when both mgmt PF and user PF are binded to one vm,"},{"line_number":71,"context_line":"  and end user can program the FPGA device."}],"source_content_type":"text/x-rst","patch_set":9,"id":"0960e64c_d90c2a38","line":68,"range":{"start_line":68,"start_character":38,"end_line":68,"end_character":66},"in_reply_to":"1dc79223_5d4b6f7e","updated":"2021-11-01 07:32:32.000000000","message":"It is unnecessary. Remove it.","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"58bf8dd8c023aea73e42866344b5cfe3b2ffc635","unresolved":true,"context_lines":[{"line_number":72,"context_line":""},{"line_number":73,"context_line":"- ``program()``: This function works by executing ``xbmgmt program`` command"},{"line_number":74,"context_line":"  which is included with the XRT installation package.[2]_ Also, this function"},{"line_number":75,"context_line":"  should be called for pre-program before binding to vm."},{"line_number":76,"context_line":""},{"line_number":77,"context_line":"Below is the objects to describe a FPGA device which"},{"line_number":78,"context_line":"complies with the Cyborg database mode and Placement data model."}],"source_content_type":"text/x-rst","patch_set":9,"id":"48dde26a_48a7509e","line":75,"updated":"2021-10-29 07:52:17.000000000","message":"if program is not support, we should doc here and support in future.","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"5483de4e5d06122c726435403c7dac434efc4310","unresolved":true,"context_lines":[{"line_number":72,"context_line":""},{"line_number":73,"context_line":"- ``program()``: This function works by executing ``xbmgmt program`` command"},{"line_number":74,"context_line":"  which is included with the XRT installation package.[2]_ Also, this function"},{"line_number":75,"context_line":"  should be called for pre-program before binding to vm."},{"line_number":76,"context_line":""},{"line_number":77,"context_line":"Below is the objects to describe a FPGA device which"},{"line_number":78,"context_line":"complies with the Cyborg database mode and Placement data model."}],"source_content_type":"text/x-rst","patch_set":9,"id":"36af08a9_3271bffc","line":75,"in_reply_to":"48dde26a_48a7509e","updated":"2021-11-01 07:32:32.000000000","message":"I want to add the support.","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"58bf8dd8c023aea73e42866344b5cfe3b2ffc635","unresolved":true,"context_lines":[{"line_number":88,"context_line":"     |               |                      |"},{"line_number":89,"context_line":"  1 FPGA       1 attach_handle    ---\u003e inventories(total:1)"},{"line_number":90,"context_line":""},{"line_number":91,"context_line":"- Add one new driver configuration \u0027xilinx_fpga_driver\u0027."},{"line_number":92,"context_line":""},{"line_number":93,"context_line":"Alternatives"},{"line_number":94,"context_line":"------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"acb03d72_bd81281f","line":91,"range":{"start_line":91,"start_character":0,"end_line":91,"end_character":56},"updated":"2021-10-29 07:52:17.000000000","message":"remove this as deployer impact already has the content.","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"5483de4e5d06122c726435403c7dac434efc4310","unresolved":false,"context_lines":[{"line_number":88,"context_line":"     |               |                      |"},{"line_number":89,"context_line":"  1 FPGA       1 attach_handle    ---\u003e inventories(total:1)"},{"line_number":90,"context_line":""},{"line_number":91,"context_line":"- Add one new driver configuration \u0027xilinx_fpga_driver\u0027."},{"line_number":92,"context_line":""},{"line_number":93,"context_line":"Alternatives"},{"line_number":94,"context_line":"------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"f44aa876_a2ee087e","line":91,"range":{"start_line":91,"start_character":0,"end_line":91,"end_character":56},"in_reply_to":"acb03d72_bd81281f","updated":"2021-11-01 07:32:32.000000000","message":"Done","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"58bf8dd8c023aea73e42866344b5cfe3b2ffc635","unresolved":true,"context_lines":[{"line_number":98,"context_line":"Data model impact"},{"line_number":99,"context_line":"-----------------"},{"line_number":100,"context_line":""},{"line_number":101,"context_line":"None"},{"line_number":102,"context_line":""},{"line_number":103,"context_line":"Xilinx FPGA driver will not touch Data model."},{"line_number":104,"context_line":"The Cyborg Agent can call Xilinx FPGA driver to update the database"}],"source_content_type":"text/x-rst","patch_set":9,"id":"45442fe8_7a0e1588","line":101,"updated":"2021-10-29 07:52:17.000000000","message":"nit","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"5483de4e5d06122c726435403c7dac434efc4310","unresolved":false,"context_lines":[{"line_number":98,"context_line":"Data model impact"},{"line_number":99,"context_line":"-----------------"},{"line_number":100,"context_line":""},{"line_number":101,"context_line":"None"},{"line_number":102,"context_line":""},{"line_number":103,"context_line":"Xilinx FPGA driver will not touch Data model."},{"line_number":104,"context_line":"The Cyborg Agent can call Xilinx FPGA driver to update the database"}],"source_content_type":"text/x-rst","patch_set":9,"id":"2835e9e4_7152d042","line":101,"in_reply_to":"45442fe8_7a0e1588","updated":"2021-11-01 07:32:32.000000000","message":"Done","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"58bf8dd8c023aea73e42866344b5cfe3b2ffc635","unresolved":true,"context_lines":[{"line_number":132,"context_line":"Other deployer impact"},{"line_number":133,"context_line":"---------------------"},{"line_number":134,"context_line":""},{"line_number":135,"context_line":"* Add one new driver configuration \u0027xilinx_fpga_driver\u0027 for agent."},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"Developer impact"},{"line_number":138,"context_line":"----------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"2c7c4b4e_97b33a65","line":135,"range":{"start_line":135,"start_character":2,"end_line":135,"end_character":66},"updated":"2021-10-29 07:52:17.000000000","message":"Add new driver xilinx_fpga_driver to enabled_drivers for agent.","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"5483de4e5d06122c726435403c7dac434efc4310","unresolved":false,"context_lines":[{"line_number":132,"context_line":"Other deployer impact"},{"line_number":133,"context_line":"---------------------"},{"line_number":134,"context_line":""},{"line_number":135,"context_line":"* Add one new driver configuration \u0027xilinx_fpga_driver\u0027 for agent."},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"Developer impact"},{"line_number":138,"context_line":"----------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dbd17de4_3dcd2a4e","line":135,"range":{"start_line":135,"start_character":2,"end_line":135,"end_character":66},"in_reply_to":"2c7c4b4e_97b33a65","updated":"2021-11-01 07:32:32.000000000","message":"Done","commit_id":"cf307ea1bec16bafe274fa77967174ceceed924f"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"f19d9645e60e90a06c63ce46da4f04bd09af6dc6","unresolved":true,"context_lines":[{"line_number":86,"context_line":"     |         1 deployable       ---\u003e resource_provider"},{"line_number":87,"context_line":"     |               |            ---\u003e parent resource_provider: compute node"},{"line_number":88,"context_line":"     |               |                      |"},{"line_number":89,"context_line":"  1 FPGA       2 attach_handle    ---\u003e inventories(total:1)"},{"line_number":90,"context_line":""},{"line_number":91,"context_line":""},{"line_number":92,"context_line":"Alternatives"}],"source_content_type":"text/x-rst","patch_set":10,"id":"3d03a401_e2d02042","line":89,"range":{"start_line":89,"start_character":15,"end_line":89,"end_character":30},"updated":"2021-11-09 09:05:57.000000000","message":"is 1 deployable has 2 ahs reasonable? and how many attributes? what\u0027s the result on your env?","commit_id":"3daa899968cb6da69723c0005befb1a01cd8394c"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"03c070e6c5da8b7bb070db7d37ff8d8686c80884","unresolved":true,"context_lines":[{"line_number":86,"context_line":"     |         1 deployable       ---\u003e resource_provider"},{"line_number":87,"context_line":"     |               |            ---\u003e parent resource_provider: compute node"},{"line_number":88,"context_line":"     |               |                      |"},{"line_number":89,"context_line":"  1 FPGA       2 attach_handle    ---\u003e inventories(total:1)"},{"line_number":90,"context_line":""},{"line_number":91,"context_line":""},{"line_number":92,"context_line":"Alternatives"}],"source_content_type":"text/x-rst","patch_set":10,"id":"72bd1ce6_d71324a4","line":89,"range":{"start_line":89,"start_character":15,"end_line":89,"end_character":30},"in_reply_to":"04a1556a_f0a349dd","updated":"2021-12-18 08:43:47.000000000","message":"looks good, remember to bind two ahs when create FPGA vm.","commit_id":"3daa899968cb6da69723c0005befb1a01cd8394c"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"8c6c5e17133c52bf3176ebc4fb270adf305b3bd7","unresolved":true,"context_lines":[{"line_number":86,"context_line":"     |         1 deployable       ---\u003e resource_provider"},{"line_number":87,"context_line":"     |               |            ---\u003e parent resource_provider: compute node"},{"line_number":88,"context_line":"     |               |                      |"},{"line_number":89,"context_line":"  1 FPGA       2 attach_handle    ---\u003e inventories(total:1)"},{"line_number":90,"context_line":""},{"line_number":91,"context_line":""},{"line_number":92,"context_line":"Alternatives"}],"source_content_type":"text/x-rst","patch_set":10,"id":"b2e2b127_8ed458fc","line":89,"range":{"start_line":89,"start_character":15,"end_line":89,"end_character":30},"in_reply_to":"3d03a401_e2d02042","updated":"2021-12-07 10:01:06.000000000","message":"In my env, there are two fpga devices.\nThe attrs:\nselect * from attributes;\n+---------------------+------------+----+--------------------------------------+---------------+--------+-----------------------------+\n| created_at          | updated_at | id | uuid                                 | deployable_id | key    | value                       |\n+---------------------+------------+----+--------------------------------------+---------------+--------+-----------------------------+\n| 2021-12-06 10:33:18 | NULL       |  3 | e6f9c225-834c-446c-bdca-e3085fe91b02 |             3 | rc     | FPGA                        |\n| 2021-12-06 10:33:18 | NULL       |  6 | 8ede446d-0982-4c42-9e81-631e03cde6e9 |             3 | trait0 | CUSTOM_FPGA_XILINX          |\n| 2021-12-06 10:33:18 | NULL       |  9 | 6779bd51-ccc3-4383-8398-444c416c5f57 |             3 | trait1 | CUSTOM_FPGA_PRODUCT_ID_5000 |\n| 2021-12-06 10:33:18 | NULL       | 12 | 5db8ad38-e65b-47a1-a99e-6f88cea8c056 |             6 | rc     | FPGA                        |\n| 2021-12-06 10:33:18 | NULL       | 15 | 42505a61-ee98-40c3-8080-7d275156128b |             6 | trait0 | CUSTOM_FPGA_XILINX          |\n| 2021-12-06 10:33:18 | NULL       | 18 | 82030dbd-c72b-4752-bba1-049c71852af7 |             6 | trait1 | CUSTOM_FPGA_PRODUCT_ID_5000 |\n+---------------------+------------+----+--------------------------------------+---------------+--------+-----------------------------+","commit_id":"3daa899968cb6da69723c0005befb1a01cd8394c"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"36c9fb5bbff12e0141949ea72ff182ec1e6615b9","unresolved":true,"context_lines":[{"line_number":86,"context_line":"     |         1 deployable       ---\u003e resource_provider"},{"line_number":87,"context_line":"     |               |            ---\u003e parent resource_provider: compute node"},{"line_number":88,"context_line":"     |               |                      |"},{"line_number":89,"context_line":"  1 FPGA       2 attach_handle    ---\u003e inventories(total:1)"},{"line_number":90,"context_line":""},{"line_number":91,"context_line":""},{"line_number":92,"context_line":"Alternatives"}],"source_content_type":"text/x-rst","patch_set":10,"id":"e3e57a9b_1d0a1162","line":89,"range":{"start_line":89,"start_character":15,"end_line":89,"end_character":30},"in_reply_to":"b2e2b127_8ed458fc","updated":"2021-12-17 07:42:57.000000000","message":"what\u0027s the ahs data in your db?","commit_id":"3daa899968cb6da69723c0005befb1a01cd8394c"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"bdf49eee4dc08a43a02a684ceb9945a9272cf663","unresolved":true,"context_lines":[{"line_number":86,"context_line":"     |         1 deployable       ---\u003e resource_provider"},{"line_number":87,"context_line":"     |               |            ---\u003e parent resource_provider: compute node"},{"line_number":88,"context_line":"     |               |                      |"},{"line_number":89,"context_line":"  1 FPGA       2 attach_handle    ---\u003e inventories(total:1)"},{"line_number":90,"context_line":""},{"line_number":91,"context_line":""},{"line_number":92,"context_line":"Alternatives"}],"source_content_type":"text/x-rst","patch_set":10,"id":"04a1556a_f0a349dd","line":89,"range":{"start_line":89,"start_character":15,"end_line":89,"end_character":30},"in_reply_to":"e3e57a9b_1d0a1162","updated":"2021-12-18 08:30:59.000000000","message":"select * from attach_handles\\G;\n*************************** 1. row ***************************\n   created_at: 2021-12-06 10:33:18\n   updated_at: 2021-12-09 02:32:19\n           id: 3\n         uuid: b9eba2d9-af07-46d3-ba4f-7b65994324c2\ndeployable_id: 3\n      cpid_id: 3\n       in_use: 0\n  attach_type: PCI\n  attach_info: {\"bus\": \"3b\", \"device\": \"00\", \"domain\": \"0000\", \"function\": \"0\"}\n*************************** 2. row ***************************\n   created_at: 2021-12-06 10:33:18\n   updated_at: 2021-12-09 02:32:19\n           id: 6\n         uuid: 18844fbd-f047-40c6-86d1-ec49e0338cf3\ndeployable_id: 3\n      cpid_id: 3\n       in_use: 0\n  attach_type: PCI\n  attach_info: {\"bus\": \"3b\", \"device\": \"00\", \"domain\": \"0000\", \"function\": \"1\"}\n*************************** 3. row ***************************\n   created_at: 2021-12-06 10:33:18\n   updated_at: NULL\n           id: 9\n         uuid: b00e560c-beac-4365-ae5f-5075322790e7\ndeployable_id: 6\n      cpid_id: 6\n       in_use: 0\n  attach_type: PCI\n  attach_info: {\"bus\": \"af\", \"device\": \"00\", \"domain\": \"0000\", \"function\": \"0\"}\n*************************** 4. row ***************************\n   created_at: 2021-12-06 10:33:18\n   updated_at: NULL\n           id: 12\n         uuid: 83968161-29c8-4384-bb26-f3a3670c0ae9\ndeployable_id: 6\n      cpid_id: 6\n       in_use: 0\n  attach_type: PCI\n  attach_info: {\"bus\": \"af\", \"device\": \"00\", \"domain\": \"0000\", \"function\": \"1\"}","commit_id":"3daa899968cb6da69723c0005befb1a01cd8394c"}]}