)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":12393,"name":"chandan kumar","display_name":"Chandan Kumar","email":"chkumar@redhat.com","username":"chkumar246"},"change_message_id":"19ff20a220ebdaadaffe5e6dd3b37fd0b37726f7","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"fe744938_fca27de1","updated":"2026-11-10 07:59:36.000000000","message":"lgtm!","commit_id":"87c1e1780e8d28c452d3227867358013dd1b8b13"}],"cyborg_tempest_plugin/tests/scenario/test_accelerator_basic_ops.py":[{"author":{"_account_id":28006,"name":"teim-ci","display_name":"teim-ci","email":"ci@seanmooney.info","username":"ci-sean-mooney","status":"this is a third-party ci account run by sean-k-mooney on irc\nhosted at zuul.teim.app"},"tag":"autogenerated:zuul:automatic-ci","change_message_id":"be388cca95711f8f104c4e033ae933e396e49dcd","unresolved":false,"context_lines":[{"line_number":182,"context_line":"        dp_name \u003d CONF.cyborg_fpga.device_profile_name"},{"line_number":183,"context_line":"        bitstream_id \u003d CONF.cyborg_fpga.bitstream_id"},{"line_number":184,"context_line":""},{"line_number":185,"context_line":"        if dp_name and bitstream_id:"},{"line_number":186,"context_line":"            # Configured driver: use the supplied device profile and"},{"line_number":187,"context_line":"            # bitstream image."},{"line_number":188,"context_line":"            pass"}],"source_content_type":"text/x-python","patch_set":2,"id":"bdc890ce_8694e5fc","line":185,"updated":"2026-11-04 20:48:51.000000000","message":"In test_fpga_program_on_bind, when both CONF.cyborg_fpga.device_profile_name and bitstream_id are set, the branch at lines 185-188 executes only `pass`; the configured bitstream_id value is never sent to Cyborg or Glance anywhere in the test. Cyborg\u0027s bind-time programming is triggered by accel:bitstream_id inside the device profile groups, as the fake-driver branch (lines 189-206) demonstrates by embedding accel:bitstream_id into the profile it creates. So in the configured mode, programming only happens if the operator\u0027s existing profile already contains that key; the new config option merely acts as a pass/fail gate whose value has no effect. This contradicts the config help text (\u0027Glance image UUID of a bitstream for bind-time programming. Required together with device_profile_name for configured drivers\u0027) and the commit message claim that \u0027the test uses them for any configured driver\u0027.\n\n**Severity**: WARNING | **Confidence**: 0.85\n\n**Impact**: An operator configuring both options (per the documented contract) gets no guarantee the test exercises bind-time programming: if their device profile lacks accel:bitstream_id, the server boots ACTIVE with no programming attempt and the smoke test passes vacuously, giving false CI confidence for exactly the scenario the option exists to configure. Conversely, setups that only configure device_profile_name (sufficient for the pre-existing test_fpga_program) now hard-fail the new test at line 209 with self.fail unless they also set a config value the test then ignores.\n\n**Suggestion**:\nMake the gate verify the contract before booting: in the configured branch, fetch the profile via self.os_admin.cyborg_client and assert its groups contain accel:bitstream_id equal to CONF.cyborg_fpga.bitstream_id, so a mismatch fails loudly instead of passing vacuously; and adjust the config help text to state that the configured device profile itself must reference this image. This is the smallest fix that makes the configured mode\u0027s pass/fail signal honest without mutating the operator\u0027s profile.","commit_id":"87e2863d8474e618dd5e43dee93fbca5fbad8a50"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"e9bc90149e603719d3d92555a361bf1c21d43f26","unresolved":true,"context_lines":[{"line_number":194,"context_line":"                        {"},{"line_number":195,"context_line":"                            \u0027resources:FPGA\u0027: \u00271\u0027,"},{"line_number":196,"context_line":"                            \u0027trait:CUSTOM_FAKE_DEVICE\u0027: \u0027required\u0027,"},{"line_number":197,"context_line":"                            \u0027accel:bitstream_id\u0027: bitstream_id,"},{"line_number":198,"context_line":"                        }"},{"line_number":199,"context_line":"                    ],"},{"line_number":200,"context_line":"                }"}],"source_content_type":"text/x-python","patch_set":3,"id":"29a0f970_829a474c","line":197,"range":{"start_line":197,"start_character":27,"end_line":197,"end_character":63},"updated":"2026-11-05 18:20:04.000000000","message":"thinking about his more, i fwe add supprot to programing a glance image to a nvme device i think we shoudl likely have tha tuse a seprte key\n\nwe woudl reserve `accel:bitstream_id` for fpga bitstreams adn the assocated semantic of updating traits\n\nand for nvme device we will probly just have\n`accel:image_uuid` or similar\n\nwhile i do not reant to add a firmware interface to cybrog that would leave the door open to supproting\n\n`accel:firmware_uuid` or similar in the future for that usecase as well in a more device indepente way.\n\n\nbased on that i think testing this only with the fake driver is correct for now and we can evaualte programign a nvme device with a glanceimage as its own top levle feature and add that to the pci sim\n\nfor the fpga case if we ant to we can add a fake FPGA device which is basiclly an alis of the nvme one if we want too. i.e. a thing to which we can write some data and make some asstions about it. i just dont knwo if that is useful addtional test coverage or not.","commit_id":"87c1e1780e8d28c452d3227867358013dd1b8b13"},{"author":{"_account_id":4690,"name":"melanie witt","display_name":"melwitt","email":"melwittt@gmail.com","username":"melwitt"},"change_message_id":"dfe580575f7bb4c94f353d629b091be276ab58f0","unresolved":true,"context_lines":[{"line_number":194,"context_line":"                        {"},{"line_number":195,"context_line":"                            \u0027resources:FPGA\u0027: \u00271\u0027,"},{"line_number":196,"context_line":"                            \u0027trait:CUSTOM_FAKE_DEVICE\u0027: \u0027required\u0027,"},{"line_number":197,"context_line":"                            \u0027accel:bitstream_id\u0027: bitstream_id,"},{"line_number":198,"context_line":"                        }"},{"line_number":199,"context_line":"                    ],"},{"line_number":200,"context_line":"                }"}],"source_content_type":"text/x-python","patch_set":3,"id":"ef4d6892_836a9cfe","line":197,"range":{"start_line":197,"start_character":27,"end_line":197,"end_character":63},"in_reply_to":"29a0f970_829a474c","updated":"2026-11-05 18:23:06.000000000","message":"Ack, thanks.","commit_id":"87c1e1780e8d28c452d3227867358013dd1b8b13"},{"author":{"_account_id":12393,"name":"chandan kumar","display_name":"Chandan Kumar","email":"chkumar@redhat.com","username":"chkumar246"},"change_message_id":"19ff20a220ebdaadaffe5e6dd3b37fd0b37726f7","unresolved":true,"context_lines":[{"line_number":194,"context_line":"                        {"},{"line_number":195,"context_line":"                            \u0027resources:FPGA\u0027: \u00271\u0027,"},{"line_number":196,"context_line":"                            \u0027trait:CUSTOM_FAKE_DEVICE\u0027: \u0027required\u0027,"},{"line_number":197,"context_line":"                            \u0027accel:bitstream_id\u0027: bitstream_id,"},{"line_number":198,"context_line":"                        }"},{"line_number":199,"context_line":"                    ],"},{"line_number":200,"context_line":"                }"}],"source_content_type":"text/x-python","patch_set":3,"id":"36177421_362446b4","line":197,"range":{"start_line":197,"start_character":27,"end_line":197,"end_character":63},"in_reply_to":"ef4d6892_836a9cfe","updated":"2026-11-10 07:59:36.000000000","message":"+1 to the idea of programign a nvme device with a glanceimage and emulating it via pci-sim, I will include it in my nvme spec for future scope.","commit_id":"87c1e1780e8d28c452d3227867358013dd1b8b13"}]}