)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":11878,"name":"Rushil Chugh","email":"rushil.chugh@gmail.com","username":"rushil"},"change_message_id":"fe90cc7e59f8619c04680556d3cfcb13017657ed","unresolved":false,"context_lines":[{"line_number":4,"context_line":"Commit:     ShaoHe Feng \u003cshaohe.feng@intel.com\u003e"},{"line_number":5,"context_line":"CommitDate: 2018-01-26 09:44:14 +0000"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"fpga driver support"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"This patch is not a plugin implementation"},{"line_number":10,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":11,"id":"5f93b717_dcb957e9","line":7,"range":{"start_line":7,"start_character":0,"end_line":7,"end_character":4},"updated":"2018-01-29 17:48:22.000000000","message":"FPGA","commit_id":"e46cea2bec81dcb97b13b03c0645e5ae922d7af6"},{"author":{"_account_id":11878,"name":"Rushil Chugh","email":"rushil.chugh@gmail.com","username":"rushil"},"change_message_id":"fe90cc7e59f8619c04680556d3cfcb13017657ed","unresolved":false,"context_lines":[{"line_number":8,"context_line":""},{"line_number":9,"context_line":"This patch is not a plugin implementation"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"Cyborg agent can call driver as follow:"},{"line_number":12,"context_line":"from cyborg.accelerator.drivers.fpga import base"},{"line_number":13,"context_line":"# There maybe more than one vendor fpga card on a host."},{"line_number":14,"context_line":"fdriver \u003d base.FPGADriver"},{"line_number":15,"context_line":"venders \u003d fdriver.discover_vendors()"},{"line_number":16,"context_line":"for v in venders:"},{"line_number":17,"context_line":"    dr \u003d fdriver.create(v)"},{"line_number":18,"context_line":"    dr.discover()"},{"line_number":19,"context_line":""},{"line_number":20,"context_line":"intel \u003d base.FPGADriver.create(\"intel\")"},{"line_number":21,"context_line":"intel.program(\"/fpga/device/path\", \"/local/path/image\")"},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"When call IntelFPGADriver.discover(), we can get the result as follow:"},{"line_number":24,"context_line":"    [{\u0027assignable\u0027: False,"},{"line_number":25,"context_line":"      \u0027devices\u0027: \u00270000:5e:00.0\u0027,"},{"line_number":26,"context_line":"      \u0027function\u0027: \u0027pf\u0027,"},{"line_number":27,"context_line":"      \u0027parent_devices\u0027: \u0027\u0027,"},{"line_number":28,"context_line":"      \u0027path\u0027: \u0027/sys/class/fpga/intel-fpga-dev.0\u0027,"},{"line_number":29,"context_line":"      \u0027pr_num\u0027: \u00271\u0027,"},{"line_number":30,"context_line":"      \u0027product_id\u0027: \u00270xbcc0\u0027,"},{"line_number":31,"context_line":"      \u0027regions\u0027: [{\u0027assignable\u0027: True,"},{"line_number":32,"context_line":"        \u0027devices\u0027: \u00270000:5e:00.1\u0027,"},{"line_number":33,"context_line":"        \u0027function\u0027: \u0027vf\u0027,"},{"line_number":34,"context_line":"        \u0027parent_devices\u0027: \u00270000:5e:00.0\u0027,"},{"line_number":35,"context_line":"        \u0027path\u0027: \u0027/sys/class/fpga/intel-fpga-dev.2\u0027,"},{"line_number":36,"context_line":"        \u0027product_id\u0027: \u00270xbcc1\u0027,"},{"line_number":37,"context_line":"        \u0027vendor_id\u0027: \u00270x8086\u0027}],"},{"line_number":38,"context_line":"      \u0027vendor_id\u0027: \u00270x8086\u0027},"},{"line_number":39,"context_line":"     {\u0027assignable\u0027: True,"},{"line_number":40,"context_line":"      \u0027devices\u0027: \u00270000:be:00.0\u0027,"},{"line_number":41,"context_line":"      \u0027function\u0027: \u0027pf\u0027,"},{"line_number":42,"context_line":"      \u0027parent_devices\u0027: \u0027\u0027,"},{"line_number":43,"context_line":"      \u0027path\u0027: \u0027/sys/class/fpga/intel-fpga-dev.1\u0027,"},{"line_number":44,"context_line":"      \u0027pr_num\u0027: \u00270\u0027,"},{"line_number":45,"context_line":"      \u0027product_id\u0027: \u00270xbcc0\u0027,"},{"line_number":46,"context_line":"      \u0027vendor_id\u0027: \u00270x8086\u0027}]"},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"Cyborg agent can use it to form it\u0027s DB."},{"line_number":49,"context_line":""},{"line_number":50,"context_line":"FPGA program should use root user."},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"Co-Authored-By: Dolpher Du \u003cDolpher.Du@intel.com\u003e"},{"line_number":53,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":11,"id":"5f93b717_5cc5475a","line":50,"range":{"start_line":11,"start_character":0,"end_line":50,"end_character":34},"updated":"2018-01-29 17:48:22.000000000","message":"This should be moved into docs and does not belong in the commit message","commit_id":"e46cea2bec81dcb97b13b03c0645e5ae922d7af6"}],"cyborg/accelerator/drivers/fpga/__init__.py":[{"author":{"_account_id":11878,"name":"Rushil Chugh","email":"rushil.chugh@gmail.com","username":"rushil"},"change_message_id":"ebbe5d37971c3b8d0fc0d4a26cfede890dcfff96","unresolved":false,"context_lines":[{"line_number":14,"context_line":""},{"line_number":15,"context_line":"import os"},{"line_number":16,"context_line":"import glob"},{"line_number":17,"context_line":""},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"__import__(\u0027pkg_resources\u0027).declare_namespace(__name__)"},{"line_number":20,"context_line":"__import__(\".\".join([__package__, \u0027base\u0027]))"}],"source_content_type":"text/x-python","patch_set":11,"id":"5f93b717_e2e28001","line":17,"updated":"2018-01-28 21:35:04.000000000","message":"Please import log here","commit_id":"e46cea2bec81dcb97b13b03c0645e5ae922d7af6"},{"author":{"_account_id":11878,"name":"Rushil Chugh","email":"rushil.chugh@gmail.com","username":"rushil"},"change_message_id":"ebbe5d37971c3b8d0fc0d4a26cfede890dcfff96","unresolved":false,"context_lines":[{"line_number":26,"context_line":"    for m in modules:"},{"line_number":27,"context_line":"        try:"},{"line_number":28,"context_line":"            __import__(m, globals(), locals(), [\u0027\u0027])"},{"line_number":29,"context_line":"            print(\"Succefully to load fpga vendor driver: %s.\" % m)"},{"line_number":30,"context_line":"        except ImportError as e:"},{"line_number":31,"context_line":"            print(\"Failed to load fpga vendor driver: %s. Details: %s\""},{"line_number":32,"context_line":"                  % (m, e))"}],"source_content_type":"text/x-python","patch_set":11,"id":"5f93b717_82f13cd0","line":29,"range":{"start_line":29,"start_character":12,"end_line":29,"end_character":17},"updated":"2018-01-28 21:35:04.000000000","message":"Make this Log.debug","commit_id":"e46cea2bec81dcb97b13b03c0645e5ae922d7af6"},{"author":{"_account_id":11878,"name":"Rushil Chugh","email":"rushil.chugh@gmail.com","username":"rushil"},"change_message_id":"ebbe5d37971c3b8d0fc0d4a26cfede890dcfff96","unresolved":false,"context_lines":[{"line_number":26,"context_line":"    for m in modules:"},{"line_number":27,"context_line":"        try:"},{"line_number":28,"context_line":"            __import__(m, globals(), locals(), [\u0027\u0027])"},{"line_number":29,"context_line":"            print(\"Succefully to load fpga vendor driver: %s.\" % m)"},{"line_number":30,"context_line":"        except ImportError as e:"},{"line_number":31,"context_line":"            print(\"Failed to load fpga vendor driver: %s. Details: %s\""},{"line_number":32,"context_line":"                  % (m, e))"}],"source_content_type":"text/x-python","patch_set":11,"id":"5f93b717_42bd74d6","line":29,"range":{"start_line":29,"start_character":19,"end_line":29,"end_character":42},"updated":"2018-01-28 21:35:04.000000000","message":"Successfully loaded FPGA","commit_id":"e46cea2bec81dcb97b13b03c0645e5ae922d7af6"},{"author":{"_account_id":11878,"name":"Rushil Chugh","email":"rushil.chugh@gmail.com","username":"rushil"},"change_message_id":"ebbe5d37971c3b8d0fc0d4a26cfede890dcfff96","unresolved":false,"context_lines":[{"line_number":28,"context_line":"            __import__(m, globals(), locals(), [\u0027\u0027])"},{"line_number":29,"context_line":"            print(\"Succefully to load fpga vendor driver: %s.\" % m)"},{"line_number":30,"context_line":"        except ImportError as e:"},{"line_number":31,"context_line":"            print(\"Failed to load fpga vendor driver: %s. Details: %s\""},{"line_number":32,"context_line":"                  % (m, e))"},{"line_number":33,"context_line":""},{"line_number":34,"context_line":""}],"source_content_type":"text/x-python","patch_set":11,"id":"5f93b717_a2ec78f3","line":31,"range":{"start_line":31,"start_character":12,"end_line":31,"end_character":17},"updated":"2018-01-28 21:35:04.000000000","message":"LOG.error","commit_id":"e46cea2bec81dcb97b13b03c0645e5ae922d7af6"}],"cyborg/accelerator/drivers/fpga/base.py":[{"author":{"_account_id":11878,"name":"Rushil Chugh","email":"rushil.chugh@gmail.com","username":"rushil"},"change_message_id":"9182aeeb89a80a27397ba172dfc7717d8b3fac76","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# Copyright 2017 Intel, Inc."},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Licensed under the Apache License, Version 2.0 (the \"License\"); you may"},{"line_number":4,"context_line":"# not use this file except in compliance with the License. You may obtain"}],"source_content_type":"text/x-python","patch_set":2,"id":"9f91af0f_0251910e","line":1,"range":{"start_line":1,"start_character":12,"end_line":1,"end_character":16},"updated":"2018-01-05 21:30:46.000000000","message":"2018","commit_id":"29624ebf13f780376f40935a7b332b9094415c49"}],"cyborg/accelerator/drivers/fpga/intel.py":[{"author":{"_account_id":11878,"name":"Rushil Chugh","email":"rushil.chugh@gmail.com","username":"rushil"},"change_message_id":"9182aeeb89a80a27397ba172dfc7717d8b3fac76","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# Copyright 2017 Intel, Inc."},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Licensed under the Apache License, Version 2.0 (the \"License\"); you may"},{"line_number":4,"context_line":"# not use this file except in compliance with the License. You may obtain"}],"source_content_type":"text/x-python","patch_set":2,"id":"9f91af0f_e24d8d72","line":1,"range":{"start_line":1,"start_character":12,"end_line":1,"end_character":16},"updated":"2018-01-05 21:30:46.000000000","message":"2018","commit_id":"29624ebf13f780376f40935a7b332b9094415c49"}],"cyborg/accelerator/drivers/fpga/intel/sysinfo.py":[{"author":{"_account_id":19853,"name":"Nguyen Hung Phuong","email":"phuongnh@vn.fujitsu.com","username":"phuongnh"},"change_message_id":"68d2059c72aa37b36936e54f3d39b8aa552e6cfd","unresolved":false,"context_lines":[{"line_number":69,"context_line":""},{"line_number":70,"context_line":"def fpga_device(path):"},{"line_number":71,"context_line":"    infos \u003d {}"},{"line_number":72,"context_line":"    def read_line(filename):"},{"line_number":73,"context_line":"        with open(filename) as f:"},{"line_number":74,"context_line":"            return f.readline().strip()"},{"line_number":75,"context_line":""}],"source_content_type":"text/x-python","patch_set":4,"id":"7f96bb07_789713ed","line":72,"updated":"2018-01-23 07:39:52.000000000","message":"please insert 1 blank line here","commit_id":"57123db75e6b06ee84661489386838673ee07c57"}],"cyborg/accelerator/drivers/fpga/util.py":[{"author":{"_account_id":11878,"name":"Rushil Chugh","email":"rushil.chugh@gmail.com","username":"rushil"},"change_message_id":"9182aeeb89a80a27397ba172dfc7717d8b3fac76","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# Copyright 2017 Intel, Inc."},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Licensed under the Apache License, Version 2.0 (the \"License\"); you may"},{"line_number":4,"context_line":"# not use this file except in compliance with the License. You may obtain"}],"source_content_type":"text/x-python","patch_set":2,"id":"9f91af0f_8237e1e3","line":1,"range":{"start_line":1,"start_character":12,"end_line":1,"end_character":16},"updated":"2018-01-05 21:30:46.000000000","message":"2018","commit_id":"29624ebf13f780376f40935a7b332b9094415c49"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"cbf4ebc32ee18f8433c775c26cb069676ed404e5","unresolved":false,"context_lines":[{"line_number":23,"context_line":""},{"line_number":24,"context_line":"VENDORS \u003d [\"intel\"]  # can extend, such as [\"intel\", \"xilinx\"]"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"SYS_FPGA_PATH \u003d \"/sys/class/fpga\""},{"line_number":27,"context_line":"VENDORS_PATTERN \u003d re.compile(\"|\".join([\"(%s)\" % v for v in VENDORS]))"},{"line_number":28,"context_line":""},{"line_number":29,"context_line":""}],"source_content_type":"text/x-python","patch_set":5,"id":"7f96bb07_b7fef335","line":26,"range":{"start_line":26,"start_character":0,"end_line":26,"end_character":33},"updated":"2018-01-23 18:46:48.000000000","message":"This way of discovery is too specific to Intel, I believe Xilinx relies on lspci command. It\u0027s better to implement a generic method here and let each Vendors to have their own way of implementation.","commit_id":"4e7e20b34b7ccc0f672ea4a977c682ef8f47bb03"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"a525adf0be3012482f606acb46d50aebb2a8631f","unresolved":false,"context_lines":[{"line_number":23,"context_line":""},{"line_number":24,"context_line":"VENDORS \u003d [\"intel\"]  # can extend, such as [\"intel\", \"xilinx\"]"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"SYS_FPGA_PATH \u003d \"/sys/class/fpga\""},{"line_number":27,"context_line":"VENDORS_PATTERN \u003d re.compile(\"|\".join([\"(%s)\" % v for v in VENDORS]))"},{"line_number":28,"context_line":""},{"line_number":29,"context_line":""}],"source_content_type":"text/x-python","patch_set":5,"id":"7f96bb07_b49a585f","line":26,"range":{"start_line":26,"start_character":0,"end_line":26,"end_character":33},"in_reply_to":"7f96bb07_b7fef335","updated":"2018-01-24 09:47:58.000000000","message":"I\u0027m not familiar use Xilinx.\nI have not Xilinx env. \n\nCan you give me some more infos about Xilinx.\n\nLet\u0027s unify the interface.","commit_id":"4e7e20b34b7ccc0f672ea4a977c682ef8f47bb03"}]}