)]}'
{"doc/specs/rocky/cyborg-fpga-bitstream-spec.rst":[{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"9df8145765757fa249fb7018341a370839618432","unresolved":false,"context_lines":[{"line_number":11,"context_line":"Blueprint url:"},{"line_number":12,"context_line":"https://blueprints.launchpad.net/openstack-cyborg/+spec/cyborg-fpga-bitstream-metadata-spec"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":"This spec proposed the FPGA Bitstream metadata specifications for bitstream"},{"line_number":15,"context_line":"management"},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"Problem description"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_2269ddf7","line":14,"range":{"start_line":14,"start_character":10,"end_line":14,"end_character":18},"updated":"2018-04-03 10:39:28.000000000","message":"proposes","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f6c3796d1f3eac31467ae05885c4f582898eee5a","unresolved":false,"context_lines":[{"line_number":21,"context_line":"configured by a customer or a designer after manufacturing. Their advantage lies"},{"line_number":22,"context_line":"in that they are sometimes significantly faster for some applications because of"},{"line_number":23,"context_line":"their parallel nature and optimality in terms of the number of gates used for a"},{"line_number":24,"context_line":"certain process. Hence, using FPGA for application acceleration in cloud has been"},{"line_number":25,"context_line":"becoming desirable. One of the encountered problems is when it comes to bitstream"},{"line_number":26,"context_line":"management, it is difficult to map bitstreams to their appropriate FPGA boards or"},{"line_number":27,"context_line":"reconfigurable regions. The aim of this proposal is to provide a standardized"},{"line_number":28,"context_line":"set of metadata which should be encapsulated together with bitstream storage."}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_8c01f007","line":25,"range":{"start_line":24,"start_character":73,"end_line":25,"end_character":8},"updated":"2018-04-13 10:07:36.000000000","message":"has become","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f6c3796d1f3eac31467ae05885c4f582898eee5a","unresolved":false,"context_lines":[{"line_number":32,"context_line":""},{"line_number":33,"context_line":"When user requests to reprogram a FPGA board with certain functionality in the"},{"line_number":34,"context_line":"cloud environment, he or she will need to retrieve a suitable bitstream from the"},{"line_number":35,"context_line":"storage. In order to find the suitable one, bitstreams need to be catagorized"},{"line_number":36,"context_line":"based on some porperties defined in metadata."},{"line_number":37,"context_line":""},{"line_number":38,"context_line":"Proposed change"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_0c15e03f","line":35,"range":{"start_line":35,"start_character":66,"end_line":35,"end_character":77},"updated":"2018-04-13 10:07:36.000000000","message":"categorized","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f6c3796d1f3eac31467ae05885c4f582898eee5a","unresolved":false,"context_lines":[{"line_number":33,"context_line":"When user requests to reprogram a FPGA board with certain functionality in the"},{"line_number":34,"context_line":"cloud environment, he or she will need to retrieve a suitable bitstream from the"},{"line_number":35,"context_line":"storage. In order to find the suitable one, bitstreams need to be catagorized"},{"line_number":36,"context_line":"based on some porperties defined in metadata."},{"line_number":37,"context_line":""},{"line_number":38,"context_line":"Proposed change"},{"line_number":39,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_2c10e44d","line":36,"range":{"start_line":36,"start_character":14,"end_line":36,"end_character":24},"updated":"2018-04-13 10:07:36.000000000","message":"properties","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f6c3796d1f3eac31467ae05885c4f582898eee5a","unresolved":false,"context_lines":[{"line_number":48,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":49,"context_line":"| name        |  value(example) |  nullable | description                              |"},{"line_number":50,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":51,"context_line":"| bs-name     |  aes-128        |  False    | name of the bitstream                    |"},{"line_number":52,"context_line":"| bs-uuid     |  {uuid}         |  False    | The uuid generated during synthesis      |"},{"line_number":53,"context_line":"| vendor      |  Xilinx         |  False    | Vendor of the card                       |"},{"line_number":54,"context_line":"| board       |  KU115          |  False    | Board type for this bitstream to load    |"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_ac0b948b","line":51,"range":{"start_line":51,"start_character":2,"end_line":51,"end_character":9},"updated":"2018-04-13 10:07:36.000000000","message":"Is this expected to be unique, like the UUID?","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"bc5212ac6dfa89b6f9839eaed04a91411d9e33c3","unresolved":false,"context_lines":[{"line_number":48,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":49,"context_line":"| name        |  value(example) |  nullable | description                              |"},{"line_number":50,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":51,"context_line":"| bs-name     |  aes-128        |  False    | name of the bitstream                    |"},{"line_number":52,"context_line":"| bs-uuid     |  {uuid}         |  False    | The uuid generated during synthesis      |"},{"line_number":53,"context_line":"| vendor      |  Xilinx         |  False    | Vendor of the card                       |"},{"line_number":54,"context_line":"| board       |  KU115          |  False    | Board type for this bitstream to load    |"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_35d26e01","line":51,"range":{"start_line":51,"start_character":2,"end_line":51,"end_character":9},"in_reply_to":"bf659307_ac0b948b","updated":"2018-04-13 21:36:38.000000000","message":"This does not need to be unique like uuids.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f6c3796d1f3eac31467ae05885c4f582898eee5a","unresolved":false,"context_lines":[{"line_number":51,"context_line":"| bs-name     |  aes-128        |  False    | name of the bitstream                    |"},{"line_number":52,"context_line":"| bs-uuid     |  {uuid}         |  False    | The uuid generated during synthesis      |"},{"line_number":53,"context_line":"| vendor      |  Xilinx         |  False    | Vendor of the card                       |"},{"line_number":54,"context_line":"| board       |  KU115          |  False    | Board type for this bitstream to load    |"},{"line_number":55,"context_line":"| shell_id    |  {uuid}         |  True     | Required shell bs-uuid for this bitstream|"},{"line_number":56,"context_line":"| version     |  1.0            |  False    | Device version number                    |"},{"line_number":57,"context_line":"| driver      |  SDX            |  False    | Type of driver for this bitstream        |"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_ccf12897","line":54,"range":{"start_line":54,"start_character":2,"end_line":54,"end_character":7},"updated":"2018-04-13 10:07:36.000000000","message":"Not clear why we need a board type etc. to check bitstream loading. Logically, we only need something that identifies the region type uniquely.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"bc5212ac6dfa89b6f9839eaed04a91411d9e33c3","unresolved":false,"context_lines":[{"line_number":51,"context_line":"| bs-name     |  aes-128        |  False    | name of the bitstream                    |"},{"line_number":52,"context_line":"| bs-uuid     |  {uuid}         |  False    | The uuid generated during synthesis      |"},{"line_number":53,"context_line":"| vendor      |  Xilinx         |  False    | Vendor of the card                       |"},{"line_number":54,"context_line":"| board       |  KU115          |  False    | Board type for this bitstream to load    |"},{"line_number":55,"context_line":"| shell_id    |  {uuid}         |  True     | Required shell bs-uuid for this bitstream|"},{"line_number":56,"context_line":"| version     |  1.0            |  False    | Device version number                    |"},{"line_number":57,"context_line":"| driver      |  SDX            |  False    | Type of driver for this bitstream        |"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_75322660","line":54,"range":{"start_line":54,"start_character":2,"end_line":54,"end_character":7},"in_reply_to":"bf659307_ccf12897","updated":"2018-04-13 21:36:38.000000000","message":"This is needed when the bitstream is targetting a specific board. e.g. A shell bitstream.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"9df8145765757fa249fb7018341a370839618432","unresolved":false,"context_lines":[{"line_number":54,"context_line":"| board       |  KU115          |  False    | Board type for this bitstream to load    |"},{"line_number":55,"context_line":"| shell_id    |  {uuid}         |  True     | Required shell bs-uuid for this bitstream|"},{"line_number":56,"context_line":"| version     |  1.0            |  False    | Device version number                    |"},{"line_number":57,"context_line":"| driver      |  SDX            |  False    | Type of driver for this bitstream        |"},{"line_number":58,"context_line":"| driver_ver  |  1.0            |  False    | Driver version                           |"},{"line_number":59,"context_line":"| driver_path |  /path/to/driver|  False    | Where to retrieve the driver binary      |"},{"line_number":60,"context_line":"| topology    |  {CLOB}         |  False    | Function Topology                        |"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_bd6e6ec6","line":57,"range":{"start_line":57,"start_character":2,"end_line":57,"end_character":8},"updated":"2018-04-03 10:39:28.000000000","message":"what is driver?\nLinux driver?","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"bc5212ac6dfa89b6f9839eaed04a91411d9e33c3","unresolved":false,"context_lines":[{"line_number":54,"context_line":"| board       |  KU115          |  False    | Board type for this bitstream to load    |"},{"line_number":55,"context_line":"| shell_id    |  {uuid}         |  True     | Required shell bs-uuid for this bitstream|"},{"line_number":56,"context_line":"| version     |  1.0            |  False    | Device version number                    |"},{"line_number":57,"context_line":"| driver      |  SDX            |  False    | Type of driver for this bitstream        |"},{"line_number":58,"context_line":"| driver_ver  |  1.0            |  False    | Driver version                           |"},{"line_number":59,"context_line":"| driver_path |  /path/to/driver|  False    | Where to retrieve the driver binary      |"},{"line_number":60,"context_line":"| topology    |  {CLOB}         |  False    | Function Topology                        |"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_35290ee5","line":57,"range":{"start_line":57,"start_character":2,"end_line":57,"end_character":8},"in_reply_to":"bf659307_6c71fca7","updated":"2018-04-13 21:36:38.000000000","message":"I can make this field nullable for now.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f6c3796d1f3eac31467ae05885c4f582898eee5a","unresolved":false,"context_lines":[{"line_number":54,"context_line":"| board       |  KU115          |  False    | Board type for this bitstream to load    |"},{"line_number":55,"context_line":"| shell_id    |  {uuid}         |  True     | Required shell bs-uuid for this bitstream|"},{"line_number":56,"context_line":"| version     |  1.0            |  False    | Device version number                    |"},{"line_number":57,"context_line":"| driver      |  SDX            |  False    | Type of driver for this bitstream        |"},{"line_number":58,"context_line":"| driver_ver  |  1.0            |  False    | Driver version                           |"},{"line_number":59,"context_line":"| driver_path |  /path/to/driver|  False    | Where to retrieve the driver binary      |"},{"line_number":60,"context_line":"| topology    |  {CLOB}         |  False    | Function Topology                        |"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_6c71fca7","line":57,"range":{"start_line":57,"start_character":2,"end_line":57,"end_character":8},"in_reply_to":"bf659307_bd6e6ec6","updated":"2018-04-13 10:07:36.000000000","message":"+1. Also, which kernel version, which distro? If Cyborg starts to manage driver software, that can get complicated!","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"086522dc97b659ab155827bfe923e8754bb07c15","unresolved":false,"context_lines":[{"line_number":54,"context_line":"| board       |  KU115          |  False    | Board type for this bitstream to load    |"},{"line_number":55,"context_line":"| shell_id    |  {uuid}         |  True     | Required shell bs-uuid for this bitstream|"},{"line_number":56,"context_line":"| version     |  1.0            |  False    | Device version number                    |"},{"line_number":57,"context_line":"| driver      |  SDX            |  False    | Type of driver for this bitstream        |"},{"line_number":58,"context_line":"| driver_ver  |  1.0            |  False    | Driver version                           |"},{"line_number":59,"context_line":"| driver_path |  /path/to/driver|  False    | Where to retrieve the driver binary      |"},{"line_number":60,"context_line":"| topology    |  {CLOB}         |  False    | Function Topology                        |"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_44f16800","line":57,"range":{"start_line":57,"start_character":2,"end_line":57,"end_character":8},"in_reply_to":"bf659307_bd6e6ec6","updated":"2018-04-04 04:19:20.000000000","message":"This specifies the path to a package of scripts/binaries to be installed in order\nto use the loaded bitstream(e.g. insmod some kernel driver/git clone some remote\nsource code, etc)","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f6c3796d1f3eac31467ae05885c4f582898eee5a","unresolved":false,"context_lines":[{"line_number":56,"context_line":"| version     |  1.0            |  False    | Device version number                    |"},{"line_number":57,"context_line":"| driver      |  SDX            |  False    | Type of driver for this bitstream        |"},{"line_number":58,"context_line":"| driver_ver  |  1.0            |  False    | Driver version                           |"},{"line_number":59,"context_line":"| driver_path |  /path/to/driver|  False    | Where to retrieve the driver binary      |"},{"line_number":60,"context_line":"| topology    |  {CLOB}         |  False    | Function Topology                        |"},{"line_number":61,"context_line":"| description |  description    |  True     | Description                              |"},{"line_number":62,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_ec43cc3d","line":59,"range":{"start_line":59,"start_character":17,"end_line":59,"end_character":32},"updated":"2018-04-13 10:07:36.000000000","message":"* This assumes that the driver is a single binary, lies in the file system, and is accessible by all compute nodes in the same path. \n* What is the purpose of this table? Are we saying that the driver code will be injected by Cyborg into the VM? If so, many operators/tenants may not want that. It would be safer to use cloud-init (or similar) to have the VM pull whatever packages it needs. This gives control to operators and tenants, and also addresses security concerns. Cyborg/Nova could inject ssh-keys to enable cloud-init.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"bc5212ac6dfa89b6f9839eaed04a91411d9e33c3","unresolved":false,"context_lines":[{"line_number":56,"context_line":"| version     |  1.0            |  False    | Device version number                    |"},{"line_number":57,"context_line":"| driver      |  SDX            |  False    | Type of driver for this bitstream        |"},{"line_number":58,"context_line":"| driver_ver  |  1.0            |  False    | Driver version                           |"},{"line_number":59,"context_line":"| driver_path |  /path/to/driver|  False    | Where to retrieve the driver binary      |"},{"line_number":60,"context_line":"| topology    |  {CLOB}         |  False    | Function Topology                        |"},{"line_number":61,"context_line":"| description |  description    |  True     | Description                              |"},{"line_number":62,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_5585a2ab","line":59,"range":{"start_line":59,"start_character":17,"end_line":59,"end_character":32},"in_reply_to":"bf659307_ec43cc3d","updated":"2018-04-13 21:36:38.000000000","message":"1. This \"table\" is not a database table. This is a table of k-v pairs that pre-negotiate with vendors for bitstream images.\n2. The driver that needs to be loaded after the bitstream is programmed is not limited to VM drivers. There are also host side drivers.\n3. In addition, cloud-init can only take care the use case where the bitstream is loaded at VM provisioning time. It won\u0027t work when the bitstream is loaded during VM runtime.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"9df8145765757fa249fb7018341a370839618432","unresolved":false,"context_lines":[{"line_number":57,"context_line":"| driver      |  SDX            |  False    | Type of driver for this bitstream        |"},{"line_number":58,"context_line":"| driver_ver  |  1.0            |  False    | Driver version                           |"},{"line_number":59,"context_line":"| driver_path |  /path/to/driver|  False    | Where to retrieve the driver binary      |"},{"line_number":60,"context_line":"| topology    |  {CLOB}         |  False    | Function Topology                        |"},{"line_number":61,"context_line":"| description |  description    |  True     | Description                              |"},{"line_number":62,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":63,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_62011506","line":60,"range":{"start_line":60,"start_character":35,"end_line":60,"end_character":40},"updated":"2018-04-03 10:39:28.000000000","message":"Is it Mandatory?","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"086522dc97b659ab155827bfe923e8754bb07c15","unresolved":false,"context_lines":[{"line_number":57,"context_line":"| driver      |  SDX            |  False    | Type of driver for this bitstream        |"},{"line_number":58,"context_line":"| driver_ver  |  1.0            |  False    | Driver version                           |"},{"line_number":59,"context_line":"| driver_path |  /path/to/driver|  False    | Where to retrieve the driver binary      |"},{"line_number":60,"context_line":"| topology    |  {CLOB}         |  False    | Function Topology                        |"},{"line_number":61,"context_line":"| description |  description    |  True     | Description                              |"},{"line_number":62,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":63,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_04dff068","line":60,"range":{"start_line":60,"start_character":35,"end_line":60,"end_character":40},"in_reply_to":"bf659307_62011506","updated":"2018-04-04 04:19:20.000000000","message":"Topology is not mandatory to fill in, as long as vendor driver can figure\nout what resources to report after the bitstream is loaded","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f6c3796d1f3eac31467ae05885c4f582898eee5a","unresolved":false,"context_lines":[{"line_number":63,"context_line":""},{"line_number":64,"context_line":"Here are the details regarding some definded keys."},{"line_number":65,"context_line":""},{"line_number":66,"context_line":"[shell_id]"},{"line_number":67,"context_line":"This field is a uuid pointing to the required shell image uuid for loading this"},{"line_number":68,"context_line":"pr bitstream. If it is null, this bitstream is a shell bitstream."},{"line_number":69,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_0cd3a005","line":66,"range":{"start_line":66,"start_character":1,"end_line":66,"end_character":9},"updated":"2018-04-13 10:07:36.000000000","message":"Why do we need to assume that a shell exists? That is true of current implementations, but are we mandating that for all implementations supported by Cyborg? Logically, we only need a region type UUID -- that must match the acrtual region type UUID in a device. \nIn a specific implementation, if there is a shell and only one region, perhaps the shell ID itself can be used to identify the region. However, that is not architecturally needed.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"bc5212ac6dfa89b6f9839eaed04a91411d9e33c3","unresolved":false,"context_lines":[{"line_number":63,"context_line":""},{"line_number":64,"context_line":"Here are the details regarding some definded keys."},{"line_number":65,"context_line":""},{"line_number":66,"context_line":"[shell_id]"},{"line_number":67,"context_line":"This field is a uuid pointing to the required shell image uuid for loading this"},{"line_number":68,"context_line":"pr bitstream. If it is null, this bitstream is a shell bitstream."},{"line_number":69,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_b532fe0e","line":66,"range":{"start_line":66,"start_character":1,"end_line":66,"end_character":9},"in_reply_to":"bf659307_0cd3a005","updated":"2018-04-13 21:36:38.000000000","message":"shell_id by itself can handle both scenarios of shell bitstream and PR bitstream. I believe combine them into 1 field can make the implementation a bit easier reduce confusion and error handling.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"922b6520f5b0e0b28726903200f42516ab82fed8","unresolved":false,"context_lines":[{"line_number":63,"context_line":""},{"line_number":64,"context_line":"Here are the details regarding some definded keys."},{"line_number":65,"context_line":""},{"line_number":66,"context_line":"[shell_id]"},{"line_number":67,"context_line":"This field is a uuid pointing to the required shell image uuid for loading this"},{"line_number":68,"context_line":"pr bitstream. If it is null, this bitstream is a shell bitstream."},{"line_number":69,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"9f6a8fd7_3a18fd7f","line":66,"range":{"start_line":66,"start_character":1,"end_line":66,"end_character":9},"in_reply_to":"bf659307_b532fe0e","updated":"2018-04-23 01:40:02.000000000","message":"When there are multiple regions within the shell, we would need a unique region type ID, for the bitstream to match. The shell ID alone would not be sufficient. We could call this field as a shell/region type ID, with another flag indicating whether the bitstream is meant to update the shell or the region within.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f6c3796d1f3eac31467ae05885c4f582898eee5a","unresolved":false,"context_lines":[{"line_number":65,"context_line":""},{"line_number":66,"context_line":"[shell_id]"},{"line_number":67,"context_line":"This field is a uuid pointing to the required shell image uuid for loading this"},{"line_number":68,"context_line":"pr bitstream. If it is null, this bitstream is a shell bitstream."},{"line_number":69,"context_line":""},{"line_number":70,"context_line":""},{"line_number":71,"context_line":"[topology]"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_ccd8481f","line":68,"range":{"start_line":68,"start_character":14,"end_line":68,"end_character":64},"updated":"2018-04-13 10:07:36.000000000","message":"It may be better to have an explicit flag that this is a shell bitstream.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f6c3796d1f3eac31467ae05885c4f582898eee5a","unresolved":false,"context_lines":[{"line_number":70,"context_line":""},{"line_number":71,"context_line":"[topology]"},{"line_number":72,"context_line":"This field describes the topology of function structures after the bitstream is"},{"line_number":73,"context_line":"loaded on the FPGA. In particular, it uses JSON format to visualize how physical"},{"line_number":74,"context_line":"functions, virtual functions are co-related to each other. It is vendor driver\u0027s"},{"line_number":75,"context_line":"responsibility to interpret this and prepare the porper report for Cyborg Agent."},{"line_number":76,"context_line":"For instance::"},{"line_number":77,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_0c8080f4","line":74,"range":{"start_line":73,"start_character":72,"end_line":74,"end_character":28},"updated":"2018-04-13 10:07:36.000000000","message":"As per the guidelines we got in the PTG, we need to move away from a PCI-centric description. That will expand the scope of Cyborg. \nPlease structure this JSON in terms of nested FPGA device, region and (region-type/function). They may be associated with PFs/VFs.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"bc5212ac6dfa89b6f9839eaed04a91411d9e33c3","unresolved":false,"context_lines":[{"line_number":70,"context_line":""},{"line_number":71,"context_line":"[topology]"},{"line_number":72,"context_line":"This field describes the topology of function structures after the bitstream is"},{"line_number":73,"context_line":"loaded on the FPGA. In particular, it uses JSON format to visualize how physical"},{"line_number":74,"context_line":"functions, virtual functions are co-related to each other. It is vendor driver\u0027s"},{"line_number":75,"context_line":"responsibility to interpret this and prepare the porper report for Cyborg Agent."},{"line_number":76,"context_line":"For instance::"},{"line_number":77,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_c04ed26d","line":74,"range":{"start_line":73,"start_character":72,"end_line":74,"end_character":28},"in_reply_to":"bf659307_0c8080f4","updated":"2018-04-13 21:36:38.000000000","message":"This JSON just provides a reference template on how the topology can look like. However, the internal context should be transparent to Cyborg. Only the vendors need to deal with it. I will and a note in the spec to point it out.","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"9df8145765757fa249fb7018341a370839618432","unresolved":false,"context_lines":[{"line_number":135,"context_line":"virtual_function"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":""},{"line_number":138,"context_line":"Finnally, all of the FPGA bitstreams should be TAGGED as \"FPGA\" in Grance. This helps"},{"line_number":139,"context_line":"distinguishing between normal VM images and bitstream images during filtering."},{"line_number":140,"context_line":""},{"line_number":141,"context_line":"Alternatives"}],"source_content_type":"text/x-rst","patch_set":1,"id":"bf659307_3d349edd","line":138,"range":{"start_line":138,"start_character":67,"end_line":138,"end_character":73},"updated":"2018-04-03 10:39:28.000000000","message":"Glance?","commit_id":"0903355a68a9390a6f1095379d398b4fb01a487f"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"922b6520f5b0e0b28726903200f42516ab82fed8","unresolved":false,"context_lines":[{"line_number":64,"context_line":"Here are the details regarding some definded keys."},{"line_number":65,"context_line":""},{"line_number":66,"context_line":"[shell_id]"},{"line_number":67,"context_line":"This field is a uuid pointing to the required shell image uuid for loading this"},{"line_number":68,"context_line":"pr bitstream. If it is null, this bitstream is a shell bitstream."},{"line_number":69,"context_line":""},{"line_number":70,"context_line":"[driver]"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_58b435d1","line":67,"range":{"start_line":67,"start_character":37,"end_line":67,"end_character":62},"updated":"2018-04-23 01:40:02.000000000","message":"1. How will this work if there are multiple regions in an FPGA? \n2. This seems to require the presence of a shell. That is true of today\u0027s implementations. But are we precluding implementations without a shell?\n3. The Cyborg-Nova scheduling spec refers to region type UUIDs, to handle above scenarios. The bitstream metadata needs to match that.","commit_id":"a48db4a0ccf771a5c43e10ca3a6dc14f80bee2fb"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"ab203cefff6fa8d30686070e8f1c011f33a99888","unresolved":false,"context_lines":[{"line_number":64,"context_line":"Here are the details regarding some definded keys."},{"line_number":65,"context_line":""},{"line_number":66,"context_line":"[shell_id]"},{"line_number":67,"context_line":"This field is a uuid pointing to the required shell image uuid for loading this"},{"line_number":68,"context_line":"pr bitstream. If it is null, this bitstream is a shell bitstream."},{"line_number":69,"context_line":""},{"line_number":70,"context_line":"[driver]"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_d9b7b4f4","line":67,"range":{"start_line":67,"start_character":37,"end_line":67,"end_character":62},"in_reply_to":"9f6a8fd7_58b435d1","updated":"2018-04-25 02:25:19.000000000","message":"Hi Sundar, I think I got your point. You are worried that for a given shell A with 2 regions x and y. With a bitstream B which is targetting to be loaded in Ax region.\nAFAIK, when writing to the flash of the FPGA, from driver\u0027s point of view, it does not care about whether this bs is for region x or y because the bitstream loading process will decode the binary and write it to the appropriate flash location. \n\nBTW, where do you get those region type UUIDs? Are they generated by Cyborg or coming with bitstreams during sythesis?\n\nIn case you want to talk about it in details and more clear, call me on WeChat :)","commit_id":"a48db4a0ccf771a5c43e10ca3a6dc14f80bee2fb"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"922b6520f5b0e0b28726903200f42516ab82fed8","unresolved":false,"context_lines":[{"line_number":68,"context_line":"pr bitstream. If it is null, this bitstream is a shell bitstream."},{"line_number":69,"context_line":""},{"line_number":70,"context_line":"[driver]"},{"line_number":71,"context_line":"This specifies the path to a package of scripts/binaries to be installed in order"},{"line_number":72,"context_line":"to use the loaded bitstream(e.g. insmod some kernel driver/git clone some remote"},{"line_number":73,"context_line":"source code, etc)"},{"line_number":74,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_18cf9d56","line":71,"range":{"start_line":71,"start_character":40,"end_line":71,"end_character":72},"updated":"2018-04-23 01:40:02.000000000","message":"How do we plan to handle the security of such drivers? Will they be authenticated/encrypted, and will Cyborg handle the decryption etc.?","commit_id":"a48db4a0ccf771a5c43e10ca3a6dc14f80bee2fb"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"ab203cefff6fa8d30686070e8f1c011f33a99888","unresolved":false,"context_lines":[{"line_number":68,"context_line":"pr bitstream. If it is null, this bitstream is a shell bitstream."},{"line_number":69,"context_line":""},{"line_number":70,"context_line":"[driver]"},{"line_number":71,"context_line":"This specifies the path to a package of scripts/binaries to be installed in order"},{"line_number":72,"context_line":"to use the loaded bitstream(e.g. insmod some kernel driver/git clone some remote"},{"line_number":73,"context_line":"source code, etc)"},{"line_number":74,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_d99a5460","line":71,"range":{"start_line":71,"start_character":40,"end_line":71,"end_character":72},"in_reply_to":"9f6a8fd7_18cf9d56","updated":"2018-04-25 02:25:19.000000000","message":"Do these scripts and drivers need to be encrypted? they are not the actual bistreams tho.","commit_id":"a48db4a0ccf771a5c43e10ca3a6dc14f80bee2fb"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"922b6520f5b0e0b28726903200f42516ab82fed8","unresolved":false,"context_lines":[{"line_number":78,"context_line":"loaded on the FPGA. In particular, it uses JSON format to visualize how physical"},{"line_number":79,"context_line":"functions, virtual functions are co-related to each other. It is vendor driver\u0027s"},{"line_number":80,"context_line":"responsibility to interpret this and prepare the porper report for Cyborg Agent."},{"line_number":81,"context_line":"For instance::"},{"line_number":82,"context_line":""},{"line_number":83,"context_line":"    {"},{"line_number":84,"context_line":"      \"pf_num\": 2,"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_782c9901","line":81,"range":{"start_line":81,"start_character":4,"end_line":81,"end_character":12},"updated":"2018-04-23 01:40:02.000000000","message":"1. Is this an example? It is not a spec, right?\n2. The bitstream metadata needs to express what functions are present, with PCI functions as attributes, along the lines of the device dictionary in agent-driver API.","commit_id":"a48db4a0ccf771a5c43e10ca3a6dc14f80bee2fb"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"ab203cefff6fa8d30686070e8f1c011f33a99888","unresolved":false,"context_lines":[{"line_number":78,"context_line":"loaded on the FPGA. In particular, it uses JSON format to visualize how physical"},{"line_number":79,"context_line":"functions, virtual functions are co-related to each other. It is vendor driver\u0027s"},{"line_number":80,"context_line":"responsibility to interpret this and prepare the porper report for Cyborg Agent."},{"line_number":81,"context_line":"For instance::"},{"line_number":82,"context_line":""},{"line_number":83,"context_line":"    {"},{"line_number":84,"context_line":"      \"pf_num\": 2,"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_f97b98f1","line":81,"range":{"start_line":81,"start_character":4,"end_line":81,"end_character":12},"in_reply_to":"9f6a8fd7_782c9901","updated":"2018-04-25 02:25:19.000000000","message":"1. Yes, this is just an example.\n2. The presenting function of the bitstream can be enclosed in this JSON.\n3. This spec only helps Cyborg to understand what the bitstream will do to the FPGA after being loaded. Since the APIs proposed in programming service spec only take bitstream_uuid to start the programming process.\n4. If the user wants to select bitstreams based on functions before they are even loaded, I believe it takes whole another spec to describe how to do that. That means a few more k-v pairs need to be added here and there might be an indexing service running somewhere.","commit_id":"a48db4a0ccf771a5c43e10ca3a6dc14f80bee2fb"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"922b6520f5b0e0b28726903200f42516ab82fed8","unresolved":false,"context_lines":[{"line_number":113,"context_line":""},{"line_number":114,"context_line":"This JSON template guides Cyborg Agent to populate vf/pf/deployable list in Cyborg."},{"line_number":115,"context_line":"Given the above JSON topology, Cyborg Driver should be able to interpret the accelerator"},{"line_number":116,"context_line":"structure as follows::"},{"line_number":117,"context_line":""},{"line_number":118,"context_line":"                             \u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":119,"context_line":"                             \u003dAccelerator\u003d"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_380b817d","line":116,"range":{"start_line":116,"start_character":13,"end_line":116,"end_character":20},"updated":"2018-04-23 01:40:02.000000000","message":"An accelerator is the basic unit that gets assigned to an instance. \nAccordingly, it corresponds to a single PF/VF. May be this is a \nmatter of terminology -- but the general model for FPGAs is this:\n   1 device: N regions\n   1 region: N accelerators  \n   1 accelerator: 1 PF/VF \nFor non-FPGA devices, \n    1 device: N accelerators\n    1 accelerator: 1 PF/VF\nI think Cyborg will treat a device, a region and accelerator as Deployable -- does that sound right?","commit_id":"a48db4a0ccf771a5c43e10ca3a6dc14f80bee2fb"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"ab203cefff6fa8d30686070e8f1c011f33a99888","unresolved":false,"context_lines":[{"line_number":113,"context_line":""},{"line_number":114,"context_line":"This JSON template guides Cyborg Agent to populate vf/pf/deployable list in Cyborg."},{"line_number":115,"context_line":"Given the above JSON topology, Cyborg Driver should be able to interpret the accelerator"},{"line_number":116,"context_line":"structure as follows::"},{"line_number":117,"context_line":""},{"line_number":118,"context_line":"                             \u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":119,"context_line":"                             \u003dAccelerator\u003d"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_397590fa","line":116,"range":{"start_line":116,"start_character":13,"end_line":116,"end_character":20},"in_reply_to":"9f6a8fd7_380b817d","updated":"2018-04-25 02:25:19.000000000","message":"accelerator is the physical existence of the hardware.\nThe basic units that get assigned are deplorables. I will make it more clear in the figure below.","commit_id":"a48db4a0ccf771a5c43e10ca3a6dc14f80bee2fb"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"a6b28ee78979a5723dd7a7e772aa98a217e5db2d","unresolved":false,"context_lines":[{"line_number":60,"context_line":"| topology     |  {CLOB}         |  False    | Function Topology                        |"},{"line_number":61,"context_line":"| description  |  description    |  True     | Description                              |"},{"line_number":62,"context_line":"| region_uuid  |  {uuid}         |  True     | The uuid for target region type          |"},{"line_number":63,"context_line":"| function_uuid|  {uuid}         |  False    | The uuid for bs function type            |"},{"line_number":64,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":65,"context_line":""},{"line_number":66,"context_line":"Here are the details regarding some definded keys."}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_463fdbb4","line":63,"updated":"2018-06-06 14:35:27.000000000","message":"Please add function name as an optional property, as we agreed in:\nhttp://eavesdrop.openstack.org/irclogs/%23openstack-cyborg/%23openstack-cyborg.2018-05-09.log.html#t2018-05-09T19:00:22","commit_id":"2c18f512f2dafbc3dcb7e1ee6b2a976fc250871e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"0e4c592b026ceacc9b8ba175a4c7dc3961cc4035","unresolved":false,"context_lines":[{"line_number":67,"context_line":""},{"line_number":68,"context_line":"[shell_id]"},{"line_number":69,"context_line":"This field is optional. If a loading this PR bitstream requires a shell image, this"},{"line_number":70,"context_line":"field specifies the shell bitstream\u0027s uuid. If it field is null, it means this"},{"line_number":71,"context_line":"bitstream is a shell bitstream."},{"line_number":72,"context_line":""},{"line_number":73,"context_line":"[driver]"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_a2b0ce8b","line":70,"updated":"2018-05-10 23:15:53.000000000","message":"Loading a PR bitstream in a region should match the region type UUID. If there is only one region, you could say the shell ID is the same as region type ID. However, conceptually, it still matches the region type ID.","commit_id":"2c18f512f2dafbc3dcb7e1ee6b2a976fc250871e"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"b4dfacc9c3f41a46c195337bc12a0bf92fba1b7f","unresolved":false,"context_lines":[{"line_number":67,"context_line":""},{"line_number":68,"context_line":"[shell_id]"},{"line_number":69,"context_line":"This field is optional. If a loading this PR bitstream requires a shell image, this"},{"line_number":70,"context_line":"field specifies the shell bitstream\u0027s uuid. If it field is null, it means this"},{"line_number":71,"context_line":"bitstream is a shell bitstream."},{"line_number":72,"context_line":""},{"line_number":73,"context_line":"[driver]"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_2106e51d","line":70,"in_reply_to":"5f7c97a3_a2b0ce8b","updated":"2018-05-12 02:00:27.000000000","message":"Here I am assuming shell is different from the region as loading a shell could give 1 or more than 1 regions.","commit_id":"2c18f512f2dafbc3dcb7e1ee6b2a976fc250871e"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"0e4c592b026ceacc9b8ba175a4c7dc3961cc4035","unresolved":false,"context_lines":[{"line_number":84,"context_line":"scheduler to match traits with appropriate bitstream."},{"line_number":85,"context_line":""},{"line_number":86,"context_line":"[topology]"},{"line_number":87,"context_line":"This field describes the topology of function structures after the bitstream is"},{"line_number":88,"context_line":"loaded on the FPGA. In particular, it uses JSON format to visualize how physical"},{"line_number":89,"context_line":"functions, virtual functions are co-related to each other. It is vendor driver\u0027s"},{"line_number":90,"context_line":"responsibility to interpret this and prepare the porper report for Cyborg Agent."}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_c26aaaeb","line":87,"updated":"2018-05-10 23:15:53.000000000","message":"Shouldn\u0027t this match the structure that the driver discovers from the FPGA hardware, as defined in agent-driver API spec? Because, whether you discover the structure before programming or after programming, it should be the same.","commit_id":"2c18f512f2dafbc3dcb7e1ee6b2a976fc250871e"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"b4dfacc9c3f41a46c195337bc12a0bf92fba1b7f","unresolved":false,"context_lines":[{"line_number":84,"context_line":"scheduler to match traits with appropriate bitstream."},{"line_number":85,"context_line":""},{"line_number":86,"context_line":"[topology]"},{"line_number":87,"context_line":"This field describes the topology of function structures after the bitstream is"},{"line_number":88,"context_line":"loaded on the FPGA. In particular, it uses JSON format to visualize how physical"},{"line_number":89,"context_line":"functions, virtual functions are co-related to each other. It is vendor driver\u0027s"},{"line_number":90,"context_line":"responsibility to interpret this and prepare the porper report for Cyborg Agent."}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_61005d02","line":87,"in_reply_to":"5f7c97a3_c26aaaeb","updated":"2018-05-12 02:00:27.000000000","message":"This field is solely used by the driver to guide the discovery.","commit_id":"2c18f512f2dafbc3dcb7e1ee6b2a976fc250871e"}]}