)]}'
{"doc/specs/rocky/cyborg-fpga-programming-proposal.rst":[{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"2cd04b7289820cedd9211f6ca695589ab1165117","unresolved":false,"context_lines":[{"line_number":32,"context_line":"---------"},{"line_number":33,"context_line":""},{"line_number":34,"context_line":"In the scenario of OpenCL, user loads the accelerators on FPGA for their application."},{"line_number":35,"context_line":"When different applications are executing on OCL environment, the accelerators will"},{"line_number":36,"context_line":"be changed from time to time. It will not be feasible to power down the entire host"},{"line_number":37,"context_line":"and change the hardware manually by lab admin. In stead, through the reprogramming"},{"line_number":38,"context_line":"service, admin can manage the functions of FPGA using a set of REST APIs."}],"source_content_type":"text/x-rst","patch_set":2,"id":"bf659307_a3b7ccd8","line":35,"range":{"start_line":35,"start_character":45,"end_line":35,"end_character":48},"updated":"2018-04-08 07:43:02.000000000","message":"abbreviation for OpenCL?","commit_id":"acf82fe39993f405ef0e1376ed90c8748df8f588"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"2cd04b7289820cedd9211f6ca695589ab1165117","unresolved":false,"context_lines":[{"line_number":47,"context_line":"programming service. The REST api should have following format::"},{"line_number":48,"context_line":""},{"line_number":49,"context_line":"    Url: {base_url}/fpga/{fpga_uuid}"},{"line_number":50,"context_line":"    Method: GET"},{"line_number":51,"context_line":"    URL Params:"},{"line_number":52,"context_line":"        None"},{"line_number":53,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"bf659307_4339103d","line":50,"range":{"start_line":50,"start_character":12,"end_line":50,"end_character":15},"updated":"2018-04-08 07:43:02.000000000","message":"I\u0027m not sure patch/put/post which is more precise. Always argument on them. \n\nBut GET is not a good at here.","commit_id":"acf82fe39993f405ef0e1376ed90c8748df8f588"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"2cd04b7289820cedd9211f6ca695589ab1165117","unresolved":false,"context_lines":[{"line_number":52,"context_line":"        None"},{"line_number":53,"context_line":""},{"line_number":54,"context_line":"    Data Params:"},{"line_number":55,"context_line":"        glance_bitstream_uuid"},{"line_number":56,"context_line":""},{"line_number":57,"context_line":"    Success Response:"},{"line_number":58,"context_line":"        PUT:"}],"source_content_type":"text/x-rst","patch_set":2,"id":"bf659307_8385e8d1","line":55,"range":{"start_line":55,"start_character":8,"end_line":55,"end_character":29},"updated":"2018-04-08 07:43:02.000000000","message":"Also usually, we use url params instead of data params for GET.","commit_id":"acf82fe39993f405ef0e1376ed90c8748df8f588"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"2cd04b7289820cedd9211f6ca695589ab1165117","unresolved":false,"context_lines":[{"line_number":57,"context_line":"    Success Response:"},{"line_number":58,"context_line":"        PUT:"},{"line_number":59,"context_line":"            Code: 200"},{"line_number":60,"context_line":"            Content: { \"msg\" : \"bitstream has been loaded successfully\"}"},{"line_number":61,"context_line":""},{"line_number":62,"context_line":"    Error Response"},{"line_number":63,"context_line":"        Code: 401 UNAUTHORIZED"}],"source_content_type":"text/x-rst","patch_set":2,"id":"bf659307_4367d052","line":60,"range":{"start_line":60,"start_character":12,"end_line":60,"end_character":19},"updated":"2018-04-08 07:43:02.000000000","message":"body?","commit_id":"acf82fe39993f405ef0e1376ed90c8748df8f588"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"2cd04b7289820cedd9211f6ca695589ab1165117","unresolved":false,"context_lines":[{"line_number":81,"context_line":"          }"},{"line_number":82,"context_line":"        });"},{"line_number":83,"context_line":""},{"line_number":84,"context_line":"Second, implement the service in Cyborg which does three tasks: 1. identify the host"},{"line_number":85,"context_line":"location of the requested FPGA/Partial Reconfiguraion(PR) Region(e.g. on which host is"},{"line_number":86,"context_line":"the board located). 2. Check if the user(API caller) has the privilige to use the"},{"line_number":87,"context_line":"given bitstream and host. 3. If the previous check passed, Cyborg sends the program"}],"source_content_type":"text/x-rst","patch_set":2,"id":"bf659307_a3c6ec15","line":84,"range":{"start_line":84,"start_character":51,"end_line":84,"end_character":62},"updated":"2018-04-08 07:43:02.000000000","message":"Conductor or API do the tasks?","commit_id":"acf82fe39993f405ef0e1376ed90c8748df8f588"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"188d15f4a7cbd8d8de9d8044a4a03ab5c1a4e2c9","unresolved":false,"context_lines":[{"line_number":81,"context_line":"          }"},{"line_number":82,"context_line":"        });"},{"line_number":83,"context_line":""},{"line_number":84,"context_line":"Second, implement the service in Cyborg which does three tasks: 1. identify the host"},{"line_number":85,"context_line":"location of the requested FPGA/Partial Reconfiguraion(PR) Region(e.g. on which host is"},{"line_number":86,"context_line":"the board located). 2. Check if the user(API caller) has the privilige to use the"},{"line_number":87,"context_line":"given bitstream and host. 3. If the previous check passed, Cyborg sends the program"}],"source_content_type":"text/x-rst","patch_set":2,"id":"bf659307_57d0a61f","line":84,"range":{"start_line":84,"start_character":51,"end_line":84,"end_character":62},"in_reply_to":"bf659307_a3c6ec15","updated":"2018-04-13 01:37:25.000000000","message":"These three tasks here are generalized working flow for the REST API mentioned above. They are not separated APIs.","commit_id":"acf82fe39993f405ef0e1376ed90c8748df8f588"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"2cd04b7289820cedd9211f6ca695589ab1165117","unresolved":false,"context_lines":[{"line_number":83,"context_line":""},{"line_number":84,"context_line":"Second, implement the service in Cyborg which does three tasks: 1. identify the host"},{"line_number":85,"context_line":"location of the requested FPGA/Partial Reconfiguraion(PR) Region(e.g. on which host is"},{"line_number":86,"context_line":"the board located). 2. Check if the user(API caller) has the privilige to use the"},{"line_number":87,"context_line":"given bitstream and host. 3. If the previous check passed, Cyborg sends the program"},{"line_number":88,"context_line":"notification to the target host with requested FPGA."},{"line_number":89,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"bf659307_835e4874","line":86,"range":{"start_line":86,"start_character":36,"end_line":86,"end_character":40},"updated":"2018-04-08 07:43:02.000000000","message":"I wonder which users have the privilige?","commit_id":"acf82fe39993f405ef0e1376ed90c8748df8f588"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"a5708ddd2bde9d879f4417df17d377f8e38f8a41","unresolved":false,"context_lines":[{"line_number":24,"context_line":"certain process. In addition, FPGA can be reprogrammed based on different applications"},{"line_number":25,"context_line":"Hence, using FPGA for application acceleration in cloud has been becoming desirable."},{"line_number":26,"context_line":"Cyborg as a management framwork for heterogeneous accelerators, tracking, deploying"},{"line_number":27,"context_line":"and reprogramming FPGAs are much needed features. Since the FPGA modelling has"},{"line_number":28,"context_line":"already been proposed in another document. This one will be focused on proposing"},{"line_number":29,"context_line":"Reporgramming Service for FPGAs in Cyborg"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"Use Cases"},{"line_number":32,"context_line":"---------"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_78649922","line":29,"range":{"start_line":27,"start_character":50,"end_line":29,"end_character":41},"updated":"2018-04-23 03:08:30.000000000","message":"Please combine them into a single sentence.","commit_id":"5443a732924fac6130f148d40bef3149434572ab"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"a5708ddd2bde9d879f4417df17d377f8e38f8a41","unresolved":false,"context_lines":[{"line_number":33,"context_line":""},{"line_number":34,"context_line":"In the scenario of OpenCL, user loads the accelerators on FPGA for their application."},{"line_number":35,"context_line":"When different applications are executing on OpenCL environment, the accelerators will"},{"line_number":36,"context_line":"be changed from time to time. It will not be feasible to power down the entire host"},{"line_number":37,"context_line":"and change the hardware manually by lab admin. In stead, through the reprogramming"},{"line_number":38,"context_line":"service, admin can manage the functions of FPGA using a set of REST APIs."},{"line_number":39,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_acfc36b5","line":36,"range":{"start_line":36,"start_character":57,"end_line":36,"end_character":83},"updated":"2018-04-23 03:08:30.000000000","message":"Why do we need to power down the host for a region reprogramming? Is this a vendor-specific requirement?","commit_id":"5443a732924fac6130f148d40bef3149434572ab"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"55df345df1427a8b5e0926b5c1cfe41389a34ac2","unresolved":false,"context_lines":[{"line_number":33,"context_line":""},{"line_number":34,"context_line":"In the scenario of OpenCL, user loads the accelerators on FPGA for their application."},{"line_number":35,"context_line":"When different applications are executing on OpenCL environment, the accelerators will"},{"line_number":36,"context_line":"be changed from time to time. It will not be feasible to power down the entire host"},{"line_number":37,"context_line":"and change the hardware manually by lab admin. In stead, through the reprogramming"},{"line_number":38,"context_line":"service, admin can manage the functions of FPGA using a set of REST APIs."},{"line_number":39,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_122687cf","line":36,"range":{"start_line":36,"start_character":57,"end_line":36,"end_character":83},"in_reply_to":"9f6a8fd7_acfc36b5","updated":"2018-04-23 19:17:42.000000000","message":"you are right. I will fit it.","commit_id":"5443a732924fac6130f148d40bef3149434572ab"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"a5708ddd2bde9d879f4417df17d377f8e38f8a41","unresolved":false,"context_lines":[{"line_number":35,"context_line":"When different applications are executing on OpenCL environment, the accelerators will"},{"line_number":36,"context_line":"be changed from time to time. It will not be feasible to power down the entire host"},{"line_number":37,"context_line":"and change the hardware manually by lab admin. In stead, through the reprogramming"},{"line_number":38,"context_line":"service, admin can manage the functions of FPGA using a set of REST APIs."},{"line_number":39,"context_line":""},{"line_number":40,"context_line":"Similarly, during the maintenance of FPGA, admin needs to update/migrate shells and"},{"line_number":41,"context_line":"bitstreams on FPGAs within data center. Cyborg Reprogramming Service will allow them"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_ec922e57","line":38,"range":{"start_line":38,"start_character":9,"end_line":38,"end_character":47},"updated":"2018-04-23 03:08:30.000000000","message":"1. If the VM is running OpenCL, and is invoking Cyborg API, why is this referring to admin?\n\n2. More importantly, OpenCL with FPGAs generally uses one kernel, AFAIK. Multi-kernel OpenCL is possible, but seems to be uncommon for FPGAs. For the single-kernel case, the bitstream ID can be included in the request, as part of FPGAaaS use case in Cyborg/Nova spec. \n\n3. To truly enable a mechanism where a running VM issues requests to reprogram the region assigned to it, many more things need to be in place: the VM would need the Deployable UUID, there needs to be a way to inform the VM that the reprogramming is done, etc. It may be simpler to have an approach that is local to the node. \n\nHowever, for shell updates initiated by the admin, this mechanism is useful. Thanks for proposing this.","commit_id":"5443a732924fac6130f148d40bef3149434572ab"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"54df100b377658359c5ccb7003ef02fd3c71733a","unresolved":false,"context_lines":[{"line_number":35,"context_line":"When different applications are executing on OpenCL environment, the accelerators will"},{"line_number":36,"context_line":"be changed from time to time. It will not be feasible to power down the entire host"},{"line_number":37,"context_line":"and change the hardware manually by lab admin. In stead, through the reprogramming"},{"line_number":38,"context_line":"service, admin can manage the functions of FPGA using a set of REST APIs."},{"line_number":39,"context_line":""},{"line_number":40,"context_line":"Similarly, during the maintenance of FPGA, admin needs to update/migrate shells and"},{"line_number":41,"context_line":"bitstreams on FPGAs within data center. Cyborg Reprogramming Service will allow them"}],"source_content_type":"text/x-rst","patch_set":3,"id":"5f7c97a3_55358ca7","line":38,"range":{"start_line":38,"start_character":9,"end_line":38,"end_character":47},"in_reply_to":"9f6a8fd7_52b5df7c","updated":"2018-05-16 18:03:02.000000000","message":"OK. This is certainly a useful API for the admin. For OpenCL, a lot more discussion needs to happen, and there may be some interesting alternatives. May be we should table it for the future. :)","commit_id":"5443a732924fac6130f148d40bef3149434572ab"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"752bfd880a55f902240acd137dcb464e212882e6","unresolved":false,"context_lines":[{"line_number":35,"context_line":"When different applications are executing on OpenCL environment, the accelerators will"},{"line_number":36,"context_line":"be changed from time to time. It will not be feasible to power down the entire host"},{"line_number":37,"context_line":"and change the hardware manually by lab admin. In stead, through the reprogramming"},{"line_number":38,"context_line":"service, admin can manage the functions of FPGA using a set of REST APIs."},{"line_number":39,"context_line":""},{"line_number":40,"context_line":"Similarly, during the maintenance of FPGA, admin needs to update/migrate shells and"},{"line_number":41,"context_line":"bitstreams on FPGAs within data center. Cyborg Reprogramming Service will allow them"}],"source_content_type":"text/x-rst","patch_set":3,"id":"5f7c97a3_dbfd2209","line":38,"range":{"start_line":38,"start_character":9,"end_line":38,"end_character":47},"in_reply_to":"9f6a8fd7_ec922e57","updated":"2018-05-18 12:18:32.000000000","message":"\u003e 1. If the VM is running OpenCL, and is invoking Cyborg API, why is\n \u003e this referring to admin?\n \u003e \n \u003e 2. More importantly, OpenCL with FPGAs generally uses one kernel,\n \u003e AFAIK. Multi-kernel OpenCL is possible, but seems to be uncommon\n \u003e for FPGAs. For the single-kernel case, the bitstream ID can be\n \u003e included in the request, as part of FPGAaaS use case in Cyborg/Nova\n \u003e spec.\n \u003e \n \u003e 3. To truly enable a mechanism where a running VM issues requests\n \u003e to reprogram the region assigned to it, many more things need to be\n \u003e in place: the VM would need the Deployable UUID, there needs to be\n \u003e a way to inform the VM that the reprogramming is done, etc. It may\n \u003e be simpler to have an approach that is local to the node.\n \u003e \n \u003e However, for shell updates initiated by the admin, this mechanism\n \u003e is useful. Thanks for proposing this.","commit_id":"5443a732924fac6130f148d40bef3149434572ab"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"55df345df1427a8b5e0926b5c1cfe41389a34ac2","unresolved":false,"context_lines":[{"line_number":35,"context_line":"When different applications are executing on OpenCL environment, the accelerators will"},{"line_number":36,"context_line":"be changed from time to time. It will not be feasible to power down the entire host"},{"line_number":37,"context_line":"and change the hardware manually by lab admin. In stead, through the reprogramming"},{"line_number":38,"context_line":"service, admin can manage the functions of FPGA using a set of REST APIs."},{"line_number":39,"context_line":""},{"line_number":40,"context_line":"Similarly, during the maintenance of FPGA, admin needs to update/migrate shells and"},{"line_number":41,"context_line":"bitstreams on FPGAs within data center. Cyborg Reprogramming Service will allow them"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_52b5df7c","line":38,"range":{"start_line":38,"start_character":9,"end_line":38,"end_character":47},"in_reply_to":"9f6a8fd7_ec922e57","updated":"2018-04-23 19:17:42.000000000","message":"Hi Sundar,\n1. admin is only one of the use cases. I will add another use case on the normal user as well.\n2. In my vision, in order to use the reprogramming api in OCL, the OCL runtime needs to add a shim layer. This layer will handle the initiation of FPGA programming as well as the ack from the server.\n3. Based on my second point, the \"shim layer\" in OCL should take care of figuring out the Deployable UUID (based on information from the upstream caller), as well as wait for the server to inform the reprogramming is done, etc.\n\nI can add some of my thoughts here. But since this is a pure programming API proposal, it should not care too much about what the upstream use case/runtime is. Those details will be in separated spec when needed.","commit_id":"5443a732924fac6130f148d40bef3149434572ab"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"a5708ddd2bde9d879f4417df17d377f8e38f8a41","unresolved":false,"context_lines":[{"line_number":46,"context_line":"First of all, Cyborg needs to add extra REST APIs to allow others to invok the"},{"line_number":47,"context_line":"programming service. The REST api should have following format::"},{"line_number":48,"context_line":""},{"line_number":49,"context_line":"    Url: {base_url}/fpga/{fpga_uuid}"},{"line_number":50,"context_line":"    Method: POST"},{"line_number":51,"context_line":"    URL Params:"},{"line_number":52,"context_line":"        None"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_8ce37234","line":49,"range":{"start_line":49,"start_character":26,"end_line":49,"end_character":35},"updated":"2018-04-23 03:08:30.000000000","message":"1. Is this the Deployable UUID assigned by Cyborg?\n2. In general, this would be a region, not an entire FPGA. For shell updates, we can target the Deployable UUID for the FPGA.","commit_id":"5443a732924fac6130f148d40bef3149434572ab"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"55df345df1427a8b5e0926b5c1cfe41389a34ac2","unresolved":false,"context_lines":[{"line_number":46,"context_line":"First of all, Cyborg needs to add extra REST APIs to allow others to invok the"},{"line_number":47,"context_line":"programming service. The REST api should have following format::"},{"line_number":48,"context_line":""},{"line_number":49,"context_line":"    Url: {base_url}/fpga/{fpga_uuid}"},{"line_number":50,"context_line":"    Method: POST"},{"line_number":51,"context_line":"    URL Params:"},{"line_number":52,"context_line":"        None"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_1261a705","line":49,"range":{"start_line":49,"start_character":26,"end_line":49,"end_character":35},"in_reply_to":"9f6a8fd7_8ce37234","updated":"2018-04-23 19:17:42.000000000","message":"1. This UUID is assigned by Cyborg.\n2. Agreed, this call is not limited to updating PRs, but also Shells.","commit_id":"5443a732924fac6130f148d40bef3149434572ab"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"a5708ddd2bde9d879f4417df17d377f8e38f8a41","unresolved":false,"context_lines":[{"line_number":91,"context_line":"Third, implement notification callee in Cyborg Agent. This should be a rpc call with"},{"line_number":92,"context_line":"following signiture::"},{"line_number":93,"context_line":""},{"line_number":94,"context_line":"    int program_fpga_with_bitstream(fpga_uuid, bitstream_uuid)"},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"The function takes both fpga_uuid and bitstream_uuid as input. It uses fpga_uuid to"},{"line_number":97,"context_line":"identify which specific FPGA/PR region is going to be programmed and uses bitstream_uuid"}],"source_content_type":"text/x-rst","patch_set":3,"id":"9f6a8fd7_ccf96ac8","line":94,"range":{"start_line":94,"start_character":36,"end_line":94,"end_character":45},"updated":"2018-04-23 03:08:30.000000000","message":"Or region UUID. It would be better to call this a Deployable UUID (for a FPGA or a region)","commit_id":"5443a732924fac6130f148d40bef3149434572ab"},{"author":{"_account_id":27458,"name":"Li Liu","email":"liliueecg@gmail.com","username":"liliu"},"change_message_id":"55df345df1427a8b5e0926b5c1cfe41389a34ac2","unresolved":false,"context_lines":[{"line_number":91,"context_line":"Third, implement notification callee in Cyborg Agent. This should be a rpc call with"},{"line_number":92,"context_line":"following signiture::"},{"line_number":93,"context_line":""},{"line_number":94,"context_line":"    int program_fpga_with_bitstream(fpga_uuid, bitstream_uuid)"},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"The function takes both fpga_uuid and bitstream_uuid as input. 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In addition, this is a"},{"line_number":106,"context_line":"synchronous meaning it will wait for the programming task to be completed and"},{"line_number":107,"context_line":"then return a status code as integer. The return code should have following"},{"line_number":108,"context_line":"interpretation::"},{"line_number":109,"context_line":""},{"line_number":110,"context_line":"+------+--------------------------------------------------------+"},{"line_number":111,"context_line":"| code | meaning                                                |"}],"source_content_type":"text/x-rst","patch_set":10,"id":"5f7c97a3_78ada6e8","line":108,"range":{"start_line":108,"start_character":14,"end_line":108,"end_character":16},"updated":"2018-06-08 07:02:22.000000000","message":"Hi Li, please delete redundant colon here, just one.","commit_id":"31f4286f1de486dfef9cfe12b3f175c4fe20a912"}]}