)]}'
{"doc/specs/rocky/cyborg-agent-driver-api.rst":[{"author":{"_account_id":7900,"name":"Tomasz Paszkowski","email":"ss7pro@gmail.com","username":"tpaszkowski"},"change_message_id":"803280d4806689858c0deb76931441a88ce649fa","unresolved":false,"context_lines":[{"line_number":132,"context_line":"    syntax (see [#Custom_traits]_)"},{"line_number":133,"context_line":""},{"line_number":134,"context_line":"* Create region type traits for each region, of the form:"},{"line_number":135,"context_line":"  ``CUSTOM_\u003ctype\u003e_\u003cvendor\u003e_REGION_\u003ctype-uuid\u003e``. Apply them to the"},{"line_number":136,"context_line":"  corresponding region RP (if nRP support exists) or the compute node RP."},{"line_number":137,"context_line":""},{"line_number":138,"context_line":"  * E.g. CUSTOM_FPGA_INTEL_REGION_\u003ctype-uuid\u003e"}],"source_content_type":"text/x-rst","patch_set":1,"id":"9f6a8fd7_02817dc3","line":135,"range":{"start_line":135,"start_character":2,"end_line":135,"end_character":45},"updated":"2018-04-20 19:51:59.000000000","message":"why we need uuid here?","commit_id":"63e37b37fed762759097f36f12d1ab7054fd2e37"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"3af2a467e81552b808adf5d354b5ae5e4c769126","unresolved":false,"context_lines":[{"line_number":132,"context_line":"    syntax (see [#Custom_traits]_)"},{"line_number":133,"context_line":""},{"line_number":134,"context_line":"* Create region type traits for each region, of the form:"},{"line_number":135,"context_line":"  ``CUSTOM_\u003ctype\u003e_\u003cvendor\u003e_REGION_\u003ctype-uuid\u003e``. Apply them to the"},{"line_number":136,"context_line":"  corresponding region RP (if nRP support exists) or the compute node RP."},{"line_number":137,"context_line":""},{"line_number":138,"context_line":"  * E.g. CUSTOM_FPGA_INTEL_REGION_\u003ctype-uuid\u003e"}],"source_content_type":"text/x-rst","patch_set":1,"id":"9f6a8fd7_ccd974f3","line":135,"range":{"start_line":135,"start_character":2,"end_line":135,"end_character":45},"in_reply_to":"9f6a8fd7_02817dc3","updated":"2018-04-21 03:46:49.000000000","message":"To match a bitstream against a region type, we need the region type UUID.","commit_id":"63e37b37fed762759097f36f12d1ab7054fd2e37"},{"author":{"_account_id":7900,"name":"Tomasz Paszkowski","email":"ss7pro@gmail.com","username":"tpaszkowski"},"change_message_id":"803280d4806689858c0deb76931441a88ce649fa","unresolved":false,"context_lines":[{"line_number":141,"context_line":"    case, replace hyphens with underscores and validate all characters."},{"line_number":142,"context_line":""},{"line_number":143,"context_line":"* Create function type traits for each function in each region, of the form:"},{"line_number":144,"context_line":"  ``CUSTOM_\u003ctype\u003e_\u003cvendor\u003e_FUNCTION_\u003cfunction-uuid\u003e``. Apply them to the"},{"line_number":145,"context_line":"  corresponding region RP (if nRP support exists) or the compute node RP."},{"line_number":146,"context_line":""},{"line_number":147,"context_line":"  * E.g. CUSTOM_FPGA_INTEL_FUNCTION_\u003cfunction-uuid\u003e"}],"source_content_type":"text/x-rst","patch_set":1,"id":"9f6a8fd7_225fe172","line":144,"updated":"2018-04-20 19:51:59.000000000","message":"why we need uuid here?","commit_id":"63e37b37fed762759097f36f12d1ab7054fd2e37"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"3af2a467e81552b808adf5d354b5ae5e4c769126","unresolved":false,"context_lines":[{"line_number":141,"context_line":"    case, replace hyphens with underscores and validate all characters."},{"line_number":142,"context_line":""},{"line_number":143,"context_line":"* Create function type traits for each function in each region, of the form:"},{"line_number":144,"context_line":"  ``CUSTOM_\u003ctype\u003e_\u003cvendor\u003e_FUNCTION_\u003cfunction-uuid\u003e``. Apply them to the"},{"line_number":145,"context_line":"  corresponding region RP (if nRP support exists) or the compute node RP."},{"line_number":146,"context_line":""},{"line_number":147,"context_line":"  * E.g. CUSTOM_FPGA_INTEL_FUNCTION_\u003cfunction-uuid\u003e"}],"source_content_type":"text/x-rst","patch_set":1,"id":"9f6a8fd7_8cdffcd4","line":144,"in_reply_to":"9f6a8fd7_225fe172","updated":"2018-04-21 03:46:49.000000000","message":"A function uuid is the most precise way of communicating what the function exactly is. A flavor can ask for a specific UUID.","commit_id":"63e37b37fed762759097f36f12d1ab7054fd2e37"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"cef4cdd0fe0401579886cedf778343c7aaedbc9a","unresolved":false,"context_lines":[{"line_number":59,"context_line":"  one region per FPGA, an instance attached to that region will be"},{"line_number":60,"context_line":"  able to access all the memory, no matter how much there is. For"},{"line_number":61,"context_line":"  non-FPGA devices like GPUs, there does not seem to be a requirement"},{"line_number":62,"context_line":"  to exose video RAM."},{"line_number":63,"context_line":""},{"line_number":64,"context_line":"Cyborg will assume and handle the following component relationships:"},{"line_number":65,"context_line":""}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_3f7c30ea","line":62,"range":{"start_line":62,"start_character":5,"end_line":62,"end_character":10},"updated":"2018-06-06 07:25:43.000000000","message":"expose.\n\nAre all GPUs form different vendor, include Intel, Nvidia and AMD not need to expose VRAM?","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f79bf53f39be8def5ee16cc26bfd78cc8bdf540d","unresolved":false,"context_lines":[{"line_number":59,"context_line":"  one region per FPGA, an instance attached to that region will be"},{"line_number":60,"context_line":"  able to access all the memory, no matter how much there is. For"},{"line_number":61,"context_line":"  non-FPGA devices like GPUs, there does not seem to be a requirement"},{"line_number":62,"context_line":"  to exose video RAM."},{"line_number":63,"context_line":""},{"line_number":64,"context_line":"Cyborg will assume and handle the following component relationships:"},{"line_number":65,"context_line":""}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_540f7c87","line":62,"range":{"start_line":62,"start_character":5,"end_line":62,"end_character":10},"in_reply_to":"5f7c97a3_3f7c30ea","updated":"2018-06-06 23:07:14.000000000","message":"I am not aware of any such requirement for Rocky. This review is meant to bring up such requirements, if any. If it is found to be necessary, adding that is not a problem.","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"d5cfdeed2511cbffd67c022a3ed44a91fe6087ad","unresolved":false,"context_lines":[{"line_number":59,"context_line":"  one region per FPGA, an instance attached to that region will be"},{"line_number":60,"context_line":"  able to access all the memory, no matter how much there is. For"},{"line_number":61,"context_line":"  non-FPGA devices like GPUs, there does not seem to be a requirement"},{"line_number":62,"context_line":"  to exose video RAM."},{"line_number":63,"context_line":""},{"line_number":64,"context_line":"Cyborg will assume and handle the following component relationships:"},{"line_number":65,"context_line":""}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_19f370a1","line":62,"range":{"start_line":62,"start_character":5,"end_line":62,"end_character":10},"in_reply_to":"5f7c97a3_540f7c87","updated":"2018-06-07 10:34:41.000000000","message":"Added it if need later.","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"cef4cdd0fe0401579886cedf778343c7aaedbc9a","unresolved":false,"context_lines":[{"line_number":120,"context_line":"  * E.g. CUSTOM_FPGA_INTEL_REGION_\u003ctype-uuid\u003e"},{"line_number":121,"context_line":""},{"line_number":122,"context_line":"  * NOTE: For UUIDs, the agent will convert all hexadecimal digits to upper"},{"line_number":123,"context_line":"    case, replace hyphens with underscores and validate all characters."},{"line_number":124,"context_line":""},{"line_number":125,"context_line":"* Create function type traits for each function in each region, of the form:"},{"line_number":126,"context_line":"  ``CUSTOM_\u003ctype\u003e_\u003cvendor\u003e_FUNCTION_\u003cfunction-uuid\u003e``. Apply them to the"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_9f86a4ba","line":123,"range":{"start_line":123,"start_character":18,"end_line":123,"end_character":43},"updated":"2018-06-06 07:25:43.000000000","message":"why we need to replace hyphens?","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"4555cb5dc225ef65b7883925a7b15d00218862d6","unresolved":false,"context_lines":[{"line_number":120,"context_line":"  * E.g. CUSTOM_FPGA_INTEL_REGION_\u003ctype-uuid\u003e"},{"line_number":121,"context_line":""},{"line_number":122,"context_line":"  * NOTE: For UUIDs, the agent will convert all hexadecimal digits to upper"},{"line_number":123,"context_line":"    case, replace hyphens with underscores and validate all characters."},{"line_number":124,"context_line":""},{"line_number":125,"context_line":"* Create function type traits for each function in each region, of the form:"},{"line_number":126,"context_line":"  ``CUSTOM_\u003ctype\u003e_\u003cvendor\u003e_FUNCTION_\u003cfunction-uuid\u003e``. Apply them to the"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_e0202b9e","line":123,"range":{"start_line":123,"start_character":18,"end_line":123,"end_character":43},"in_reply_to":"5f7c97a3_590fa887","updated":"2018-06-07 16:43:31.000000000","message":"Yes, for programming prior to instance launch, we may need to get function/region UUIDs from the traits in the request. We would convert the underscores back to hyphens for that. That should be 1 line in python.","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f79bf53f39be8def5ee16cc26bfd78cc8bdf540d","unresolved":false,"context_lines":[{"line_number":120,"context_line":"  * E.g. CUSTOM_FPGA_INTEL_REGION_\u003ctype-uuid\u003e"},{"line_number":121,"context_line":""},{"line_number":122,"context_line":"  * NOTE: For UUIDs, the agent will convert all hexadecimal digits to upper"},{"line_number":123,"context_line":"    case, replace hyphens with underscores and validate all characters."},{"line_number":124,"context_line":""},{"line_number":125,"context_line":"* Create function type traits for each function in each region, of the form:"},{"line_number":126,"context_line":"  ``CUSTOM_\u003ctype\u003e_\u003cvendor\u003e_FUNCTION_\u003cfunction-uuid\u003e``. Apply them to the"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_b44db0c5","line":123,"range":{"start_line":123,"start_character":18,"end_line":123,"end_character":43},"in_reply_to":"5f7c97a3_9f86a4ba","updated":"2018-06-06 23:07:14.000000000","message":"Custom RC names have a specific syntax, given by the JSON schema in this doc:\nhttps://specs.openstack.org/openstack/nova-specs/specs/ocata/implemented/custom-resource-classes.html\nHyphens are not allowed.","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"d5cfdeed2511cbffd67c022a3ed44a91fe6087ad","unresolved":false,"context_lines":[{"line_number":120,"context_line":"  * E.g. CUSTOM_FPGA_INTEL_REGION_\u003ctype-uuid\u003e"},{"line_number":121,"context_line":""},{"line_number":122,"context_line":"  * NOTE: For UUIDs, the agent will convert all hexadecimal digits to upper"},{"line_number":123,"context_line":"    case, replace hyphens with underscores and validate all characters."},{"line_number":124,"context_line":""},{"line_number":125,"context_line":"* Create function type traits for each function in each region, of the form:"},{"line_number":126,"context_line":"  ``CUSTOM_\u003ctype\u003e_\u003cvendor\u003e_FUNCTION_\u003cfunction-uuid\u003e``. Apply them to the"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_590fa887","line":123,"range":{"start_line":123,"start_character":18,"end_line":123,"end_character":43},"in_reply_to":"5f7c97a3_b44db0c5","updated":"2018-06-07 10:34:41.000000000","message":"GOT it, thanks.\nBut with underscores, it is hard for us to extract uuid.\n\nAnother question do we need to extract uuid from RC names?","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"cef4cdd0fe0401579886cedf778343c7aaedbc9a","unresolved":false,"context_lines":[{"line_number":136,"context_line":"Data model impact"},{"line_number":137,"context_line":"-----------------"},{"line_number":138,"context_line":""},{"line_number":139,"context_line":"None"},{"line_number":140,"context_line":""},{"line_number":141,"context_line":"REST API impact"},{"line_number":142,"context_line":"---------------"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_9f7464d2","line":139,"range":{"start_line":139,"start_character":0,"end_line":139,"end_character":4},"updated":"2018-06-06 07:25:43.000000000","message":"No Data model impact? \nWhere we update the regions info to deployable?","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"d5cfdeed2511cbffd67c022a3ed44a91fe6087ad","unresolved":false,"context_lines":[{"line_number":136,"context_line":"Data model impact"},{"line_number":137,"context_line":"-----------------"},{"line_number":138,"context_line":""},{"line_number":139,"context_line":"None"},{"line_number":140,"context_line":""},{"line_number":141,"context_line":"REST API impact"},{"line_number":142,"context_line":"---------------"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_b9fb5c45","line":139,"range":{"start_line":139,"start_character":0,"end_line":139,"end_character":4},"in_reply_to":"5f7c97a3_9f1a0d6d","updated":"2018-06-07 10:34:41.000000000","message":"where do we store the regions info: region-type-uuid, \"bitstream-id\" and \"function-uuid\" in Data model? \n\nOK, we can add it later.","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f79bf53f39be8def5ee16cc26bfd78cc8bdf540d","unresolved":false,"context_lines":[{"line_number":136,"context_line":"Data model impact"},{"line_number":137,"context_line":"-----------------"},{"line_number":138,"context_line":""},{"line_number":139,"context_line":"None"},{"line_number":140,"context_line":""},{"line_number":141,"context_line":"REST API impact"},{"line_number":142,"context_line":"---------------"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_9f1a0d6d","line":139,"range":{"start_line":139,"start_character":0,"end_line":139,"end_character":4},"in_reply_to":"5f7c97a3_9f7464d2","updated":"2018-06-06 23:07:14.000000000","message":"That is the same as today.","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"4555cb5dc225ef65b7883925a7b15d00218862d6","unresolved":false,"context_lines":[{"line_number":136,"context_line":"Data model impact"},{"line_number":137,"context_line":"-----------------"},{"line_number":138,"context_line":""},{"line_number":139,"context_line":"None"},{"line_number":140,"context_line":""},{"line_number":141,"context_line":"REST API impact"},{"line_number":142,"context_line":"---------------"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_c06def99","line":139,"range":{"start_line":139,"start_character":0,"end_line":139,"end_character":4},"in_reply_to":"5f7c97a3_b9fb5c45","updated":"2018-06-07 16:43:31.000000000","message":"Done","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"cef4cdd0fe0401579886cedf778343c7aaedbc9a","unresolved":false,"context_lines":[{"line_number":189,"context_line":""},{"line_number":190,"context_line":"None"},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"Testing"},{"line_number":193,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":194,"context_line":""},{"line_number":195,"context_line":"None"},{"line_number":196,"context_line":""},{"line_number":197,"context_line":"Documentation Impact"},{"line_number":198,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_df6adceb","line":195,"range":{"start_line":192,"start_character":0,"end_line":195,"end_character":4},"updated":"2018-06-06 07:25:43.000000000","message":"No Testing?","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"4555cb5dc225ef65b7883925a7b15d00218862d6","unresolved":false,"context_lines":[{"line_number":189,"context_line":""},{"line_number":190,"context_line":"None"},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"Testing"},{"line_number":193,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":194,"context_line":""},{"line_number":195,"context_line":"None"},{"line_number":196,"context_line":""},{"line_number":197,"context_line":"Documentation Impact"},{"line_number":198,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_8067f7b7","line":195,"range":{"start_line":192,"start_character":0,"end_line":195,"end_character":4},"in_reply_to":"5f7c97a3_198290a6","updated":"2018-06-07 16:43:31.000000000","message":"Done","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"d5cfdeed2511cbffd67c022a3ed44a91fe6087ad","unresolved":false,"context_lines":[{"line_number":189,"context_line":""},{"line_number":190,"context_line":"None"},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"Testing"},{"line_number":193,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":194,"context_line":""},{"line_number":195,"context_line":"None"},{"line_number":196,"context_line":""},{"line_number":197,"context_line":"Documentation Impact"},{"line_number":198,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_198290a6","line":195,"range":{"start_line":192,"start_character":0,"end_line":195,"end_character":4},"in_reply_to":"5f7c97a3_1f7cbd70","updated":"2018-06-07 10:34:41.000000000","message":"OK, it is better to update this spec as follow:\n\nTesting\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nWill update the currently unit tests","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"},{"author":{"_account_id":21672,"name":"Sundar Nadathur","email":"sundar.nadathur@intel.com","username":"nsundar"},"change_message_id":"f79bf53f39be8def5ee16cc26bfd78cc8bdf540d","unresolved":false,"context_lines":[{"line_number":189,"context_line":""},{"line_number":190,"context_line":"None"},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"Testing"},{"line_number":193,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":194,"context_line":""},{"line_number":195,"context_line":"None"},{"line_number":196,"context_line":""},{"line_number":197,"context_line":"Documentation Impact"},{"line_number":198,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":5,"id":"5f7c97a3_1f7cbd70","line":195,"range":{"start_line":192,"start_character":0,"end_line":195,"end_character":4},"in_reply_to":"5f7c97a3_df6adceb","updated":"2018-06-06 23:07:14.000000000","message":"That is the same testing framework as today. We have unit tests like this one:\nhttp://git.openstack.org/cgit/openstack/cyborg/tree/cyborg/tests/unit/agent/test_resource_tracker.py#n63 \nWhen this spec is implemented, these unit tests will get updated. But this spec requires no new testing framework.","commit_id":"91924ed1e2f96e30eec5b2e4b3cc5358a32cff30"}]}