)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":26458,"name":"Brin Zhang","email":"zhangbailin@inspur.com","username":"zhangbailin"},"change_message_id":"17d64193a15741130b29289ea674aef062f341e5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"ba7653d0_03cb8fef","updated":"2021-12-20 06:00:45.000000000","message":"That code looks good to me, please update it\u0027s test result in https://docs.openstack.org/cyborg/latest/reference/support-matrix.html#driver-support","commit_id":"d3c138125ad5a5602064cbfdcffef7e822f86966"},{"author":{"_account_id":26458,"name":"Brin Zhang","email":"zhangbailin@inspur.com","username":"zhangbailin"},"change_message_id":"fd39456220767076d38752cfad43e4ec36ab33b8","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"1a361966_95f76bce","updated":"2022-08-16 05:35:10.000000000","message":"Eric, regarding legacy issues, is there anything you need to synchronize?","commit_id":"2c2ab34ee31409928bfdca77c1d7d9114765cf43"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"993aa26a82031fd2a76a73d3c734e9855689bd5b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"f928f842_b8920c24","updated":"2022-02-18 00:47:09.000000000","message":"LGTM","commit_id":"2c2ab34ee31409928bfdca77c1d7d9114765cf43"},{"author":{"_account_id":26458,"name":"Brin Zhang","email":"zhangbailin@inspur.com","username":"zhangbailin"},"change_message_id":"13f59b8587c6fa72d1e7028eafab75bc6a69dd50","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"b6a43566_3420a866","updated":"2022-02-18 02:48:11.000000000","message":"LGTM, there are some questions left on our meeting, I would like to have a detail discuss with vmaccel contributors on PTG or in today meeting, then to approve it if there is nothing need to update.","commit_id":"2c2ab34ee31409928bfdca77c1d7d9114765cf43"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"0037fb2f7b8a5a590bf410d8877d77bd59c898fa","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"cc1a6e71_cefd6bf1","in_reply_to":"1a361966_95f76bce","updated":"2022-08-16 11:03:51.000000000","message":"Brin, nothing from myside.","commit_id":"2c2ab34ee31409928bfdca77c1d7d9114765cf43"}],"cyborg/accelerator/drivers/fpga/xilinx/sysinfo.py":[{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"bfbe8e0deecf15dd41f555c3f8acbd78b031b4b1","unresolved":true,"context_lines":[{"line_number":72,"context_line":"    : param vendor_id: vendor_id of FPGA"},{"line_number":73,"context_line":"    : param product_id: product_id of FPGA"},{"line_number":74,"context_line":"    Example FPGA traits:"},{"line_number":75,"context_line":"    {traits:[\"CUSTOM_FPGA_XILINX\", \"CUSTOM_FPGA_PRODUCT_ID_5001\"]}"},{"line_number":76,"context_line":"    \"\"\""},{"line_number":77,"context_line":"    traits \u003d []"},{"line_number":78,"context_line":"    traits.append(\"CUSTOM_FPGA_\" + VENDOR_MAPS.get(vendor_id, \"\").upper())"}],"source_content_type":"text/x-python","patch_set":4,"id":"e32fe8e9_4a8b5632","line":75,"range":{"start_line":75,"start_character":26,"end_line":75,"end_character":32},"updated":"2021-12-30 01:39:41.000000000","message":"vendor_id or vendor_name?","commit_id":"02d95ec747e0b2032e6dd44f763439c406a3caf2"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"adafd4db4c63ebe1aedc65a3488ac9c7ea393196","unresolved":false,"context_lines":[{"line_number":72,"context_line":"    : param vendor_id: vendor_id of FPGA"},{"line_number":73,"context_line":"    : param product_id: product_id of FPGA"},{"line_number":74,"context_line":"    Example FPGA traits:"},{"line_number":75,"context_line":"    {traits:[\"CUSTOM_FPGA_XILINX\", \"CUSTOM_FPGA_PRODUCT_ID_5001\"]}"},{"line_number":76,"context_line":"    \"\"\""},{"line_number":77,"context_line":"    traits \u003d []"},{"line_number":78,"context_line":"    traits.append(\"CUSTOM_FPGA_\" + VENDOR_MAPS.get(vendor_id, \"\").upper())"}],"source_content_type":"text/x-python","patch_set":4,"id":"c98daa09_1af902c9","line":75,"range":{"start_line":75,"start_character":26,"end_line":75,"end_character":32},"in_reply_to":"e32fe8e9_4a8b5632","updated":"2021-12-30 13:26:49.000000000","message":"vendor_name got from VENDOR_MAPS by vendor_id","commit_id":"02d95ec747e0b2032e6dd44f763439c406a3caf2"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"bfbe8e0deecf15dd41f555c3f8acbd78b031b4b1","unresolved":true,"context_lines":[{"line_number":98,"context_line":"            # 0000:3b:00.0/1"},{"line_number":99,"context_line":"            is_existed \u003d False"},{"line_number":100,"context_line":"            new_addr \u003d pci_dict.get(\u0027pci_addr\u0027)"},{"line_number":101,"context_line":"            for fpga in fpga_devices:"},{"line_number":102,"context_line":"                existed_addr \u003d fpga.get(\u0027pci_addr\u0027)"},{"line_number":103,"context_line":"                # compare domain:bus:slot"},{"line_number":104,"context_line":"                if new_addr.split(\u0027.\u0027)[0] \u003d\u003d existed_addr.split(\u0027.\u0027)[0]:"},{"line_number":105,"context_line":"                    fpga.update({\u0027pci_addr\u0027: [existed_addr, new_addr]})"},{"line_number":106,"context_line":"                    is_existed \u003d True"},{"line_number":107,"context_line":"            if not is_existed:"},{"line_number":108,"context_line":"                traits \u003d _generate_traits(pci_dict[\"vendor_id\"],"},{"line_number":109,"context_line":"                                          pci_dict[\"product_id\"])"}],"source_content_type":"text/x-python","patch_set":4,"id":"cca0fe71_12ea0159","line":106,"range":{"start_line":101,"start_character":0,"end_line":106,"end_character":37},"updated":"2021-12-30 01:39:41.000000000","message":"could you pls add ut for this condition?","commit_id":"02d95ec747e0b2032e6dd44f763439c406a3caf2"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"adafd4db4c63ebe1aedc65a3488ac9c7ea393196","unresolved":false,"context_lines":[{"line_number":98,"context_line":"            # 0000:3b:00.0/1"},{"line_number":99,"context_line":"            is_existed \u003d False"},{"line_number":100,"context_line":"            new_addr \u003d pci_dict.get(\u0027pci_addr\u0027)"},{"line_number":101,"context_line":"            for fpga in fpga_devices:"},{"line_number":102,"context_line":"                existed_addr \u003d fpga.get(\u0027pci_addr\u0027)"},{"line_number":103,"context_line":"                # compare domain:bus:slot"},{"line_number":104,"context_line":"                if new_addr.split(\u0027.\u0027)[0] \u003d\u003d existed_addr.split(\u0027.\u0027)[0]:"},{"line_number":105,"context_line":"                    fpga.update({\u0027pci_addr\u0027: [existed_addr, new_addr]})"},{"line_number":106,"context_line":"                    is_existed \u003d True"},{"line_number":107,"context_line":"            if not is_existed:"},{"line_number":108,"context_line":"                traits \u003d _generate_traits(pci_dict[\"vendor_id\"],"},{"line_number":109,"context_line":"                                          pci_dict[\"product_id\"])"}],"source_content_type":"text/x-python","patch_set":4,"id":"cbd19b45_597b3bfa","line":106,"range":{"start_line":101,"start_character":0,"end_line":106,"end_character":37},"in_reply_to":"cca0fe71_12ea0159","updated":"2021-12-30 13:26:49.000000000","message":"Done\n\nThis condition will generate two ahs. Add the ut for it.","commit_id":"02d95ec747e0b2032e6dd44f763439c406a3caf2"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"c29a6f98529a4d3484b0c1f833fafe32d2f2494a","unresolved":true,"context_lines":[{"line_number":168,"context_line":"    LOG.debug(\"Xilinx fpga devices from lspci: %s\", fpga_pci_devices)"},{"line_number":169,"context_line":"    # In the return pci devices, mgmt pf and user pf are two entries."},{"line_number":170,"context_line":"    # Now only when binding both to vm, end user can program it."},{"line_number":171,"context_line":"    # So combine these two entries into one device."},{"line_number":172,"context_line":"    for fpga in _combine_device_by_pci_func(fpga_pci_devices):"},{"line_number":173,"context_line":"        driver_device_obj \u003d driver_device.DriverDevice()"},{"line_number":174,"context_line":"        driver_device_obj.vendor \u003d fpga[\"vendor_id\"]"}],"source_content_type":"text/x-python","patch_set":6,"id":"b0de040a_5fb31a81","line":171,"range":{"start_line":171,"start_character":0,"end_line":171,"end_character":51},"updated":"2021-12-31 09:46:10.000000000","message":"how one device generate two attach handles?","commit_id":"cb21b0e56101025f4b35489fbd637f9f85a5696b"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"89e7730f350bb57946823321f3ca1edb11276914","unresolved":true,"context_lines":[{"line_number":168,"context_line":"    LOG.debug(\"Xilinx fpga devices from lspci: %s\", fpga_pci_devices)"},{"line_number":169,"context_line":"    # In the return pci devices, mgmt pf and user pf are two entries."},{"line_number":170,"context_line":"    # Now only when binding both to vm, end user can program it."},{"line_number":171,"context_line":"    # So combine these two entries into one device."},{"line_number":172,"context_line":"    for fpga in _combine_device_by_pci_func(fpga_pci_devices):"},{"line_number":173,"context_line":"        driver_device_obj \u003d driver_device.DriverDevice()"},{"line_number":174,"context_line":"        driver_device_obj.vendor \u003d fpga[\"vendor_id\"]"}],"source_content_type":"text/x-python","patch_set":6,"id":"5849396d_0ea8e143","line":171,"range":{"start_line":171,"start_character":0,"end_line":171,"end_character":51},"in_reply_to":"b0de040a_5fb31a81","updated":"2022-01-01 00:49:40.000000000","message":"In _combine_device_by_pci_func()\n# compare domain:bus:slot\nif existed_addr and \\\n¦   new_addr.split(\u0027.\u0027)[0] \u003d\u003d existed_addr.split(\u0027.\u0027)[0]:\n¦   fpga.update({\u0027pci_addr\u0027: [existed_addr, new_addr]})\n¦   is_existed \u003d True","commit_id":"cb21b0e56101025f4b35489fbd637f9f85a5696b"}],"cyborg/api/controllers/v2/arqs.py":[{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"7911cffc116c494acad08b5fb669cc10e32cb4ca","unresolved":true,"context_lines":[{"line_number":139,"context_line":"            # resources should multiply by 2 cause that end user can program"},{"line_number":140,"context_line":"            # the device only when both MGMT and USER PF are bound to"},{"line_number":141,"context_line":"            # instance."},{"line_number":142,"context_line":"            if group.get(\"trait:CUSTOM_FPGA_XILINX\") \u003d\u003d \"required\":"},{"line_number":143,"context_line":"                accel_resources \u003d [int(group.get(\"resources:FPGA\")) * 2]"},{"line_number":144,"context_line":"            else:"},{"line_number":145,"context_line":"                accel_resources \u003d ["},{"line_number":146,"context_line":"                    int(val) for key, val in group.items()"},{"line_number":147,"context_line":"                    if key.startswith(\u0027resources\u0027)]"},{"line_number":148,"context_line":""},{"line_number":149,"context_line":"            # If/when we introduce non-accelerator resources, like"},{"line_number":150,"context_line":"            # device-local memory, the key search above needs to be"}],"source_content_type":"text/x-python","patch_set":8,"id":"aacc5266_88e73915","line":147,"range":{"start_line":142,"start_character":0,"end_line":147,"end_character":51},"updated":"2022-01-08 07:31:08.000000000","message":"the two accel_resources should merged. better to add ut please.","commit_id":"c2b5327a1a944cdca5af1eb8440f989261d253cf"}],"cyborg/tests/unit/accelerator/drivers/fpga/xilinx/test_driver.py":[{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"bfbe8e0deecf15dd41f555c3f8acbd78b031b4b1","unresolved":true,"context_lines":[{"line_number":27,"context_line":"def fake_output(arg):"},{"line_number":28,"context_line":"    print(arg)"},{"line_number":29,"context_line":"    if arg \u003d\u003d [\u0027lspci\u0027, \u0027-nnn\u0027, \u0027-D\u0027]:"},{"line_number":30,"context_line":"        print(\"111\")"},{"line_number":31,"context_line":"        return XILINX_FPGA_INFO"},{"line_number":32,"context_line":"    else:"},{"line_number":33,"context_line":"        return XILINX_FPGA_KERNEL_INFO"}],"source_content_type":"text/x-python","patch_set":4,"id":"aa6a0da8_0661984d","line":30,"range":{"start_line":30,"start_character":0,"end_line":30,"end_character":20},"updated":"2021-12-30 01:39:41.000000000","message":"pls remove this code.","commit_id":"02d95ec747e0b2032e6dd44f763439c406a3caf2"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"adafd4db4c63ebe1aedc65a3488ac9c7ea393196","unresolved":false,"context_lines":[{"line_number":27,"context_line":"def fake_output(arg):"},{"line_number":28,"context_line":"    print(arg)"},{"line_number":29,"context_line":"    if arg \u003d\u003d [\u0027lspci\u0027, \u0027-nnn\u0027, \u0027-D\u0027]:"},{"line_number":30,"context_line":"        print(\"111\")"},{"line_number":31,"context_line":"        return XILINX_FPGA_INFO"},{"line_number":32,"context_line":"    else:"},{"line_number":33,"context_line":"        return XILINX_FPGA_KERNEL_INFO"}],"source_content_type":"text/x-python","patch_set":4,"id":"4ba86624_45ec31f2","line":30,"range":{"start_line":30,"start_character":0,"end_line":30,"end_character":20},"in_reply_to":"aa6a0da8_0661984d","updated":"2021-12-30 13:26:49.000000000","message":"Done","commit_id":"02d95ec747e0b2032e6dd44f763439c406a3caf2"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"bfbe8e0deecf15dd41f555c3f8acbd78b031b4b1","unresolved":true,"context_lines":[{"line_number":51,"context_line":"             \u0027attach_info\u0027: \u0027{\"bus\": \"3b\", \u0027"},{"line_number":52,"context_line":"                            \u0027\"device\": \"00\", \u0027"},{"line_number":53,"context_line":"                            \u0027\"domain\": \"0000\", \u0027"},{"line_number":54,"context_line":"                            \u0027\"function\": \"0\"}\u0027,"},{"line_number":55,"context_line":"             \u0027in_use\u0027: False}"},{"line_number":56,"context_line":"        ]"},{"line_number":57,"context_line":"        attribute_list \u003d ["}],"source_content_type":"text/x-python","patch_set":4,"id":"28ef8979_cbf8bd16","line":54,"range":{"start_line":54,"start_character":29,"end_line":54,"end_character":44},"updated":"2021-12-30 01:39:41.000000000","message":"please add `\"function\": \"1\"` test as talked in the spec.","commit_id":"02d95ec747e0b2032e6dd44f763439c406a3caf2"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"adafd4db4c63ebe1aedc65a3488ac9c7ea393196","unresolved":false,"context_lines":[{"line_number":51,"context_line":"             \u0027attach_info\u0027: \u0027{\"bus\": \"3b\", \u0027"},{"line_number":52,"context_line":"                            \u0027\"device\": \"00\", \u0027"},{"line_number":53,"context_line":"                            \u0027\"domain\": \"0000\", \u0027"},{"line_number":54,"context_line":"                            \u0027\"function\": \"0\"}\u0027,"},{"line_number":55,"context_line":"             \u0027in_use\u0027: False}"},{"line_number":56,"context_line":"        ]"},{"line_number":57,"context_line":"        attribute_list \u003d ["}],"source_content_type":"text/x-python","patch_set":4,"id":"2c888f0a_0f8dd6e7","line":54,"range":{"start_line":54,"start_character":29,"end_line":54,"end_character":44},"in_reply_to":"28ef8979_cbf8bd16","updated":"2021-12-30 13:26:49.000000000","message":"Done","commit_id":"02d95ec747e0b2032e6dd44f763439c406a3caf2"},{"author":{"_account_id":31412,"name":"Wenping Song","email":"songwenping@inspur.com","username":"songwenping"},"change_message_id":"c29a6f98529a4d3484b0c1f833fafe32d2f2494a","unresolved":true,"context_lines":[{"line_number":1,"context_line":"# Copyright 2021 Xilinx, Inc."},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Licensed under the Apache License, Version 2.0 (the \"License\"); you may"},{"line_number":4,"context_line":"# not use this file except in compliance with the License. You may obtain"}],"source_content_type":"text/x-python","patch_set":6,"id":"5fba8838_8b94786f","line":1,"range":{"start_line":1,"start_character":17,"end_line":1,"end_character":23},"updated":"2021-12-31 09:46:10.000000000","message":"Inspur?","commit_id":"cb21b0e56101025f4b35489fbd637f9f85a5696b"},{"author":{"_account_id":23950,"name":"Eric Xie","email":"eric_xiett@163.com","username":"ericxie"},"change_message_id":"89e7730f350bb57946823321f3ca1edb11276914","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# Copyright 2021 Xilinx, Inc."},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Licensed under the Apache License, Version 2.0 (the \"License\"); you may"},{"line_number":4,"context_line":"# not use this file except in compliance with the License. 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