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For information on how to proceed, see\nhttps://docs.opendev.org/opendev/infra-manual/latest/developers.html#automated-testing\nand https://docs.openstack.org/project-team-guide/testing.html#how-to-handle-test-failures\n\nhttps://zuul.opendev.org/t/openstack/buildset/e95cdb87b3a04238b9a2932acf790b23\n\n- openstack-tox-cover https://zuul.opendev.org/t/openstack/build/cb2238fcf54d456a959cd0abafdcc722 : SUCCESS in 3m 25s\n- build-openstack-releasenotes https://zuul.opendev.org/t/openstack/build/ab294bdca2da4e64a5ab55a433fe7441 : SUCCESS in 2m 13s\n- openstack-tox-docs https://zuul.opendev.org/t/openstack/build/5d07409dd26c47c995b29f90d7ef76f0 : SUCCESS in 7m 43s\n- openstack-tox-pep8 https://zuul.opendev.org/t/openstack/build/21aa050efaa44f36b5ecba61fe994b75 : SUCCESS in 5m 35s\n- openstack-tox-py311 https://zuul.opendev.org/t/openstack/build/ce8ddad1638f456fb8c724866696699f : SUCCESS in 4m 44s\n- openstack-tox-py313 https://zuul.opendev.org/t/openstack/build/9606dfc38030453ea5cf92d66f59389f : SUCCESS in 4m 06s\n- openstack-tox-py314 https://zuul.opendev.org/t/openstack/build/a3ca338d03554fdb9e23d47f1fa9a0e2 : SUCCESS in 6m 43s (non-voting)\n- openstack-tox-functional https://zuul.opendev.org/t/openstack/build/325f9969e01a4020aeb3bbaf8f3eff01 : SUCCESS in 3m 47s\n- cyborg-tempest-py3 https://zuul.opendev.org/t/openstack/build/27a41013fbb34098a83ffdea10a997b6 : FAILURE in 17m 41s\n- cyborg-tempest-ipv6 https://zuul.opendev.org/t/openstack/build/3ccb4a63f3c94cdabe2ef68e7b6b4ab2 : FAILURE in 13m 04s\n- cyborg-tempest-pci-sim-nvme https://zuul.opendev.org/t/openstack/build/10d3a43b1923409bb816cc8e9efd68de : FAILURE in 9m 59s (non-voting)\n- cyborg-grenade https://zuul.opendev.org/t/openstack/build/905f750823174861b795df5516e5f1e5 : SUCCESS in 1h 04m 42s\n- cyborg-grenade-skip-level-always https://zuul.opendev.org/t/openstack/build/22540c3202944687a1752e05b2fa5567 : SUCCESS in 59m 39s\n- cyborg-tempest-srbac https://zuul.opendev.org/t/openstack/build/aa6b42105a2f4e47bf059d5d7b5cff36 : FAILURE in 26m 56s","accounts_in_message":[],"_revision_number":2},{"id":"4bc9d08238ec872cee3aeb606945310ad600be12","tag":"autogenerated:gerrit:abandon","author":{"_account_id":12393,"name":"chandan kumar","display_name":"Chandan Kumar","email":"chkumar@redhat.com","username":"chkumar246"},"date":"2026-07-30 07:20:49.000000000","message":"Abandoned","accounts_in_message":[],"_revision_number":2}],"current_revision_number":2,"current_revision":"86e4eaabed0928aa4b4e38c765f55b969a7cfa2d","revisions":{"6417360bc21a276a2535f569ca139ecdd9e2ad8d":{"kind":"REWORK","_number":1,"created":"2026-07-29 14:01:47.000000000","uploader":{"_account_id":12393,"name":"chandan kumar","display_name":"Chandan Kumar","email":"chkumar@redhat.com","username":"chkumar246"},"ref":"refs/changes/26/999126/1","fetch":{"anonymous http":{"url":"https://review.opendev.org/openstack/cyborg","ref":"refs/changes/26/999126/1","commands":{"Checkout":"git fetch https://review.opendev.org/openstack/cyborg refs/changes/26/999126/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.opendev.org/openstack/cyborg refs/changes/26/999126/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.opendev.org/openstack/cyborg refs/changes/26/999126/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.opendev.org/openstack/cyborg refs/changes/26/999126/1"}}},"commit":{"parents":[{"commit":"17606fcaa020af418d190cca9ff3573a094b4ff3","subject":"pci-sim: introduce personality ops-table dispatch for VF device types","web_links":[{"name":"gitea","tooltip":"Open in GitWeb","url":"https://opendev.org/openstack/cyborg/commit/17606fcaa020af418d190cca9ff3573a094b4ff3"}]}],"author":{"name":"Chandan Kumar (raukadah)","email":"chkumar@redhat.com","date":"2026-06-25 15:05:19.000000000","tz":330},"committer":{"name":"Chandan Kumar (raukadah)","email":"chkumar@redhat.com","date":"2026-07-29 14:00:02.000000000","tz":330},"subject":"pci-sim: add NVMe 1.4 controller ops-table personality","message":"pci-sim: add NVMe 1.4 controller ops-table personality\n\nThe pci-sim module only emulates UART (16550) devices, which limits\nCI coverage to serial-class accelerators.  OpenStack Cyborg\u0027s NVMe\naccelerator management path has no way to exercise device assignment\nend-to-end without real hardware.\n\nThis commit registers an NVMe personality in the ops-table dispatch\nframework introduced by the previous commit.  The new\npci_sim_nvme_ops structure implements bar_rw, vfio_open, vfio_close,\ninit_vf_config, and get_bar_info callbacks, making the NVMe\nemulation core available to the generic VFIO layer without any\npersonality-specific code in fake_pci_sriov_vfio.c.\n\nThe NVMe controller emulates NVMe 1.4 with file-backed storage\n(kernel_read/kernel_write on per-VF backing files, sized by\nnvme_ns_size_mb).  Supported admin commands: Identify\nController/Namespace, Create/Delete IO CQ/SQ, Set/Get Features,\nGet Log Page, Format NVM, and Sanitize.  Supported I/O commands:\nRead, Write, Write Zeroes, and Flush.  VF config space advertises\nPCI class 0x010802 (NVMe) with an MSI-X capability (33 vectors:\n1 admin + 32 I/O queues).\n\nTwo host-visibility modes are provided:\n\nPhase 1 -- char device interface:\n/dev/pci_sim_nvmeN exposes NVMe admin and I/O commands via ioctls\n(NVME_IOCTL_ADMIN_CMD, NVME_IOCTL_IO_CMD) without requiring the\nstock nvme driver.  A dedicated PCI driver\n(pci_sim_nvme_host_driver) probes NVMe-class VFs and registers a\ncharacter device per function.\n\nPhase 2 -- stock nvme driver binding via memmap BAR0:\nWhen nvme_memmap_start and nvme_memmap_size module parameters point\nto boot-time reserved memory (memmap\u003dSIZE$START), VF BAR0 addresses\nare backed by real RAM.  A polling kthread dispatches register and\ndoorbell writes from memory-mapped BAR0 to the NVMe emulation core.\nIRQ injection uses msi_get_virq + irq_retrigger (requires bare\nmetal, not hypervisor-emulated APIC).  The stock nvme driver probes\nVFs and exposes /dev/nvmeXnY block devices.\n\nAdmin queue creation is deferred from CC.ENABLE to the first\ndoorbell poll to prevent a soft lockup when rebinding from\npci_sim_vfio_pci to the stock nvme driver, because AQA/ASQ/ACQ\nare not yet written to BAR0 at CC.ENABLE time.\n\nIntegration with existing code:\n\n- fake_pci_sriov_cfg.c: BAR size is now personality-driven via\n  get_bar_info() instead of the hardcoded BAR0_SIZE constant.\n  init_msix_capability() is added for NVMe VF config space.  The\n  sriov_configure path handles poll kthread lifecycle.\n- fake_pci_sriov_core.c: NVMe module parameters (nvme_ns_size_mb,\n  nvme_backing_file, nvme_memmap_start, nvme_memmap_size) are\n  defined.  Module init/exit registers the NVMe host char device\n  driver and ioremaps the memmap region when configured.\n- fake_pci_sriov_uart.c: VF id_table switches to class_mask\n  matching (serial 0x070002 and vendor 0xff0000) so NVMe-class VFs\n  are not claimed by the UART driver.\n- fake_pci_sriov.h: NVMe class constant, BAR0 size, MSI-X cap\n  offset, Phase 2 host fields (bar0_mapped, nvme_state, poll\n  kthread), and NVMe module param externs are declared.\n\nDevStack: PCI_SIM_DEVICES\u003d\"nova:uart,cyborg:nvme\" creates PFs with\nper-service personality mapping.\n\nCI: cyborg-tempest-pci-sim-nvme Zuul job runs in Phase 1 (char\ndevice) mode for VM compatibility.\n\nGenerated-By: Claude Opus 4.6\nChange-Id: Ic3b41cc36c8c144a9d9f4b3eb9193a9b1ab828eb\nSigned-off-by: Chandan Kumar (raukadah) \u003cchkumar@redhat.com\u003e\n","web_links":[{"name":"gitea","tooltip":"Open in GitWeb","url":"https://opendev.org/openstack/cyborg/commit/6417360bc21a276a2535f569ca139ecdd9e2ad8d"}],"resolve_conflicts_web_links":[{"name":"gitea","tooltip":"Open in GitWeb","url":"https://opendev.org/openstack/cyborg/commit/6417360bc21a276a2535f569ca139ecdd9e2ad8d"}]},"branch":"refs/heads/master"},"86e4eaabed0928aa4b4e38c765f55b969a7cfa2d":{"kind":"REWORK","_number":2,"created":"2026-07-29 15:07:40.000000000","uploader":{"_account_id":12393,"name":"chandan kumar","display_name":"Chandan Kumar","email":"chkumar@redhat.com","username":"chkumar246"},"ref":"refs/changes/26/999126/2","fetch":{"anonymous http":{"url":"https://review.opendev.org/openstack/cyborg","ref":"refs/changes/26/999126/2","commands":{"Checkout":"git fetch https://review.opendev.org/openstack/cyborg refs/changes/26/999126/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.opendev.org/openstack/cyborg refs/changes/26/999126/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.opendev.org/openstack/cyborg refs/changes/26/999126/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.opendev.org/openstack/cyborg refs/changes/26/999126/2"}}},"commit":{"parents":[{"commit":"b327dfd9f958fe315bd0eafe36f2941b311dda12","subject":"pci-sim: introduce personality ops-table dispatch for VF device types","web_links":[{"name":"gitea","tooltip":"Open in GitWeb","url":"https://opendev.org/openstack/cyborg/commit/b327dfd9f958fe315bd0eafe36f2941b311dda12"}]}],"author":{"name":"Chandan Kumar (raukadah)","email":"chkumar@redhat.com","date":"2026-06-25 15:05:19.000000000","tz":330},"committer":{"name":"Chandan Kumar (raukadah)","email":"chkumar@redhat.com","date":"2026-07-29 15:06:18.000000000","tz":330},"subject":"pci-sim: add NVMe 1.4 controller ops-table personality","message":"pci-sim: add NVMe 1.4 controller ops-table personality\n\nThe pci-sim module only emulates UART (16550) devices, which limits\nCI coverage to serial-class accelerators.  OpenStack Cyborg\u0027s NVMe\naccelerator management path has no way to exercise device assignment\nend-to-end without real hardware.\n\nThis commit registers an NVMe personality in the ops-table dispatch\nframework introduced by the previous commit.  The new\npci_sim_nvme_ops structure implements bar_rw, vfio_open, vfio_close,\ninit_vf_config, and get_bar_info callbacks, making the NVMe\nemulation core available to the generic VFIO layer without any\npersonality-specific code in fake_pci_sriov_vfio.c.\n\nThe NVMe controller emulates NVMe 1.4 with file-backed storage\n(kernel_read/kernel_write on per-VF backing files, sized by\nnvme_ns_size_mb).  Supported admin commands: Identify\nController/Namespace, Create/Delete IO CQ/SQ, Set/Get Features,\nGet Log Page, Format NVM, and Sanitize.  Supported I/O commands:\nRead, Write, Write Zeroes, and Flush.  VF config space advertises\nPCI class 0x010802 (NVMe) with an MSI-X capability (33 vectors:\n1 admin + 32 I/O queues).\n\nTwo host-visibility modes are provided:\n\nPhase 1 -- char device interface:\n/dev/pci_sim_nvmeN exposes NVMe admin and I/O commands via ioctls\n(NVME_IOCTL_ADMIN_CMD, NVME_IOCTL_IO_CMD) without requiring the\nstock nvme driver.  A dedicated PCI driver\n(pci_sim_nvme_host_driver) probes NVMe-class VFs and registers a\ncharacter device per function.\n\nPhase 2 -- stock nvme driver binding via memmap BAR0:\nWhen nvme_memmap_start and nvme_memmap_size module parameters point\nto boot-time reserved memory (memmap\u003dSIZE$START), VF BAR0 addresses\nare backed by real RAM.  A polling kthread dispatches register and\ndoorbell writes from memory-mapped BAR0 to the NVMe emulation core.\nIRQ injection uses msi_get_virq + irq_retrigger (requires bare\nmetal, not hypervisor-emulated APIC).  The stock nvme driver probes\nVFs and exposes /dev/nvmeXnY block devices.\n\nAdmin queue creation is deferred from CC.ENABLE to the first\ndoorbell poll to prevent a soft lockup when rebinding from\npci_sim_vfio_pci to the stock nvme driver, because AQA/ASQ/ACQ\nare not yet written to BAR0 at CC.ENABLE time.\n\nIntegration with existing code:\n\n- fake_pci_sriov_cfg.c: BAR size is now personality-driven via\n  get_bar_info() instead of the hardcoded BAR0_SIZE constant.\n  init_msix_capability() is added for NVMe VF config space.  The\n  sriov_configure path handles poll kthread lifecycle.\n- fake_pci_sriov_core.c: NVMe module parameters (nvme_ns_size_mb,\n  nvme_backing_file, nvme_memmap_start, nvme_memmap_size) are\n  defined.  Module init/exit registers the NVMe host char device\n  driver and ioremaps the memmap region when configured.\n- fake_pci_sriov_uart.c: VF id_table switches to class_mask\n  matching (serial 0x070002 and vendor 0xff0000) so NVMe-class VFs\n  are not claimed by the UART driver.\n- fake_pci_sriov.h: NVMe class constant, BAR0 size, MSI-X cap\n  offset, Phase 2 host fields (bar0_mapped, nvme_state, poll\n  kthread), and NVMe module param externs are declared.\n\nDevStack: PCI_SIM_DEVICES\u003d\"nova:uart,cyborg:nvme\" creates PFs with\nper-service personality mapping.\n\nCI: cyborg-tempest-pci-sim-nvme Zuul job runs in Phase 1 (char\ndevice) mode for VM compatibility.\n\nGenerated-By: Claude Opus 4.6\nChange-Id: Ic3b41cc36c8c144a9d9f4b3eb9193a9b1ab828eb\nSigned-off-by: Chandan Kumar (raukadah) \u003cchkumar@redhat.com\u003e\n","web_links":[{"name":"gitea","tooltip":"Open in GitWeb","url":"https://opendev.org/openstack/cyborg/commit/86e4eaabed0928aa4b4e38c765f55b969a7cfa2d"}],"resolve_conflicts_web_links":[{"name":"gitea","tooltip":"Open in GitWeb","url":"https://opendev.org/openstack/cyborg/commit/86e4eaabed0928aa4b4e38c765f55b969a7cfa2d"}]},"branch":"refs/heads/master"}},"requirements":[],"submit_records":[],"submit_requirements":[{"name":"Verified","description":"Verified in gate by CI","status":"UNSATISFIED","is_legacy":false,"submittability_expression_result":{"expression":"label:Verified\u003dMAX AND -label:Verified\u003dMIN","fulfilled":false,"status":"FAIL","passing_atoms":[],"failing_atoms":["label:Verified\u003dMAX","label:Verified\u003dMIN"],"atom_explanations":{"label:Verified\u003dMAX":"","label:Verified\u003dMIN":""}}},{"name":"Code-Review","description":"Code reviewed by core reviewer","status":"UNSATISFIED","is_legacy":false,"submittability_expression_result":{"expression":"label:Code-Review\u003dMAX AND -label:Code-Review\u003dMIN","fulfilled":false,"status":"FAIL","passing_atoms":[],"failing_atoms":["label:Code-Review\u003dMAX","label:Code-Review\u003dMIN"],"atom_explanations":{"label:Code-Review\u003dMAX":"","label:Code-Review\u003dMIN":""}}},{"name":"Workflow","description":"Approved for gate by core reviewer","status":"UNSATISFIED","is_legacy":false,"submittability_expression_result":{"expression":"label:Workflow\u003dMAX AND -label:Workflow\u003dMIN","fulfilled":false,"status":"FAIL","passing_atoms":[],"failing_atoms":["label:Workflow\u003dMAX","label:Workflow\u003dMIN"],"atom_explanations":{"label:Workflow\u003dMAX":"","label:Workflow\u003dMIN":""}}}]}