)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":5890,"name":"Doug Goldstein","email":"cardoe@cardoe.com","username":"cardoe"},"change_message_id":"cd7b9c6686a75edda1fbf83fd53fe738078f9fe9","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":7,"id":"216843ad_f9d044f7","updated":"2026-07-10 22:24:31.000000000","message":"Can we get this out of etherpad which can be changed without history or deleted and into the wiki?","commit_id":"46a5ef8239effc83fa4ee29927491eb9ac110ad8"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"4c842d48478301fcc38f797fd331de01815e7113","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"aaa9b85b_8b7bacf7","updated":"2026-07-10 22:14:59.000000000","message":"Hi @chen.ke14@zte.com.cn\n\nThank you very much for starting the openstack-discuss mailing thread discussion in addition to keeping the etherpad and the contacts for the SIG updated. I think discussions may pick up slowly. Members of the OpenStack Technical Committee have been in touch with the RISC-V foundation governing board and there is some overlapping interest. If you don\u0027t hear from them on the openstack-discuss email list soon, they may just show up in a different venue and collaborate.\n\nI think for a SIG to be successful, you will need some sort of ongoing activity. The etherpad is a good place for you to leave content. However, please direct all public communication to the openstack-discuss email list, or, a dedicated IRC channel. That\u0027s where most of the community would be. If you need to create a dedicated channel, see https://docs.opendev.org/opendev/system-config/latest/irc.html for the steps on registering a channel and onboarding it to accessbot, gerritbot, and logging.\n\nI\u0027d encourage other TC members to vote as well so we can get this merged and make the SIG official","commit_id":"46a5ef8239effc83fa4ee29927491eb9ac110ad8"},{"author":{"_account_id":5890,"name":"Doug Goldstein","email":"cardoe@cardoe.com","username":"cardoe"},"change_message_id":"013dd03ef39407763915fbbc4b46d06536f4b2a6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"d1bb6167_ff502c7d","in_reply_to":"216843ad_f9d044f7","updated":"2026-07-13 13:42:49.000000000","message":"Done","commit_id":"46a5ef8239effc83fa4ee29927491eb9ac110ad8"},{"author":{"_account_id":28619,"name":"Dmitriy Rabotyagov","email":"noonedeadpunk@gmail.com","username":"noonedeadpunk"},"change_message_id":"2cd2ade9241f5e5687ee31a83033bf359a05e1e0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"b558bb85_2152827c","updated":"2026-07-14 17:12:20.000000000","message":"I would really love this SIG to sustain itself, as the goal for it is really a nice one. And won\u0027t become inactive right after approval and some initial activity...","commit_id":"6dd9ea6057ee2a10bf66edfbbbc2a86d4e41315a"}],"reference/sigs/sigs.yaml":[{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"042157e996e51827ba19f5b9065321fccb0f650d","unresolved":true,"context_lines":[{"line_number":280,"context_line":"  chairs:"},{"line_number":281,"context_line":"    - name: Xiang Li"},{"line_number":282,"context_line":"      irc: shawnlee1976"},{"line_number":283,"context_line":"      wechat: dgb_lee"},{"line_number":284,"context_line":"      email: li.xiang2@zte.com.cn"},{"line_number":285,"context_line":"      working language: Mandarin"},{"line_number":286,"context_line":"    - name: TBD"}],"source_content_type":"text/x-yaml","patch_set":2,"id":"f0b89d88_4fdb5d72","line":283,"updated":"2026-06-17 21:29:59.000000000","message":"this is good info.. we don\u0027t have a schema for this YAML file, so adding arbitrary fields is okay.. but, it\u0027ll not show up in the website; we can address that separately.","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":28748,"name":"chenker","email":"chen.ke14@zte.com.cn","username":"chenke"},"change_message_id":"0bc7e0112555a26e3f32cab802d430324343e5e5","unresolved":false,"context_lines":[{"line_number":280,"context_line":"  chairs:"},{"line_number":281,"context_line":"    - name: Xiang Li"},{"line_number":282,"context_line":"      irc: shawnlee1976"},{"line_number":283,"context_line":"      wechat: dgb_lee"},{"line_number":284,"context_line":"      email: li.xiang2@zte.com.cn"},{"line_number":285,"context_line":"      working language: Mandarin"},{"line_number":286,"context_line":"    - name: TBD"}],"source_content_type":"text/x-yaml","patch_set":2,"id":"49c78209_99911a64","line":283,"in_reply_to":"f0b89d88_4fdb5d72","updated":"2026-07-06 09:05:25.000000000","message":"Done","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"042157e996e51827ba19f5b9065321fccb0f650d","unresolved":true,"context_lines":[{"line_number":282,"context_line":"      irc: shawnlee1976"},{"line_number":283,"context_line":"      wechat: dgb_lee"},{"line_number":284,"context_line":"      email: li.xiang2@zte.com.cn"},{"line_number":285,"context_line":"      working language: Mandarin"},{"line_number":286,"context_line":"    - name: TBD"},{"line_number":287,"context_line":"      irc: "},{"line_number":288,"context_line":"      wechat: "}],"source_content_type":"text/x-yaml","patch_set":2,"id":"1ae506cc_2b380552","line":285,"range":{"start_line":285,"start_character":6,"end_line":285,"end_character":22},"updated":"2026-06-17 21:29:59.000000000","message":"YAML allows spaces in keys, so this is valid. But it\u0027s unconventional and inconsistent. maybe make this \"working-language\"","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"de395ec4e2acf71a8921912b11ffd44264c66e4f","unresolved":false,"context_lines":[{"line_number":282,"context_line":"      irc: shawnlee1976"},{"line_number":283,"context_line":"      wechat: dgb_lee"},{"line_number":284,"context_line":"      email: li.xiang2@zte.com.cn"},{"line_number":285,"context_line":"      working language: Mandarin"},{"line_number":286,"context_line":"    - name: TBD"},{"line_number":287,"context_line":"      irc: "},{"line_number":288,"context_line":"      wechat: "}],"source_content_type":"text/x-yaml","patch_set":2,"id":"6fca3c19_ac66cc06","line":285,"range":{"start_line":285,"start_character":6,"end_line":285,"end_character":22},"in_reply_to":"1ae506cc_2b380552","updated":"2026-06-23 21:41:50.000000000","message":"Done","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"042157e996e51827ba19f5b9065321fccb0f650d","unresolved":true,"context_lines":[{"line_number":283,"context_line":"      wechat: dgb_lee"},{"line_number":284,"context_line":"      email: li.xiang2@zte.com.cn"},{"line_number":285,"context_line":"      working language: Mandarin"},{"line_number":286,"context_line":"    - name: TBD"},{"line_number":287,"context_line":"      irc: "},{"line_number":288,"context_line":"      wechat: "},{"line_number":289,"context_line":"      email: "},{"line_number":290,"context_line":"      working language: English"},{"line_number":291,"context_line":"  scope: \u003e"},{"line_number":292,"context_line":"    RISC-V is a free and open instruction set architecture (ISA). In recent years, "},{"line_number":293,"context_line":"    a growing number of manufacturers have focused on the development of server-grade"}],"source_content_type":"text/x-yaml","patch_set":2,"id":"fd886568_62d72b86","line":290,"range":{"start_line":286,"start_character":0,"end_line":290,"end_character":31},"updated":"2026-06-17 21:29:59.000000000","message":"Are there any plans to get someone here. We can\u0027t merge this without it; i\u0027d drop this if there are currently no candidates for this","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"de395ec4e2acf71a8921912b11ffd44264c66e4f","unresolved":false,"context_lines":[{"line_number":283,"context_line":"      wechat: dgb_lee"},{"line_number":284,"context_line":"      email: li.xiang2@zte.com.cn"},{"line_number":285,"context_line":"      working language: Mandarin"},{"line_number":286,"context_line":"    - name: TBD"},{"line_number":287,"context_line":"      irc: "},{"line_number":288,"context_line":"      wechat: "},{"line_number":289,"context_line":"      email: "},{"line_number":290,"context_line":"      working language: English"},{"line_number":291,"context_line":"  scope: \u003e"},{"line_number":292,"context_line":"    RISC-V is a free and open instruction set architecture (ISA). In recent years, "},{"line_number":293,"context_line":"    a growing number of manufacturers have focused on the development of server-grade"}],"source_content_type":"text/x-yaml","patch_set":2,"id":"b6103cee_5d99deb8","line":290,"range":{"start_line":286,"start_character":0,"end_line":290,"end_character":31},"in_reply_to":"fd886568_62d72b86","updated":"2026-06-23 21:41:50.000000000","message":"Done","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"042157e996e51827ba19f5b9065321fccb0f650d","unresolved":true,"context_lines":[{"line_number":289,"context_line":"      email: "},{"line_number":290,"context_line":"      working language: English"},{"line_number":291,"context_line":"  scope: \u003e"},{"line_number":292,"context_line":"    RISC-V is a free and open instruction set architecture (ISA). In recent years, "},{"line_number":293,"context_line":"    a growing number of manufacturers have focused on the development of server-grade"},{"line_number":294,"context_line":"    RISC-V CPUs. This suggests that RISC-V may become a mainstream CPU architecture "},{"line_number":295,"context_line":"    for cloud infrastructure in the future, alongside X86 and ARM. This SIG is "}],"source_content_type":"text/x-yaml","patch_set":2,"id":"15832dd3_0d8401f3","line":292,"range":{"start_line":292,"start_character":69,"end_line":292,"end_character":75},"updated":"2026-06-17 21:29:59.000000000","message":"please trim the trailing whitespaces in each of these lines","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"de395ec4e2acf71a8921912b11ffd44264c66e4f","unresolved":false,"context_lines":[{"line_number":289,"context_line":"      email: "},{"line_number":290,"context_line":"      working language: English"},{"line_number":291,"context_line":"  scope: \u003e"},{"line_number":292,"context_line":"    RISC-V is a free and open instruction set architecture (ISA). In recent years, "},{"line_number":293,"context_line":"    a growing number of manufacturers have focused on the development of server-grade"},{"line_number":294,"context_line":"    RISC-V CPUs. This suggests that RISC-V may become a mainstream CPU architecture "},{"line_number":295,"context_line":"    for cloud infrastructure in the future, alongside X86 and ARM. This SIG is "}],"source_content_type":"text/x-yaml","patch_set":2,"id":"171bb38c_971366dc","line":292,"range":{"start_line":292,"start_character":69,"end_line":292,"end_character":75},"in_reply_to":"15832dd3_0d8401f3","updated":"2026-06-23 21:41:50.000000000","message":"Done","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"042157e996e51827ba19f5b9065321fccb0f650d","unresolved":true,"context_lines":[{"line_number":297,"context_line":"    open source projects, including OpenStack, and promoting the development of the "},{"line_number":298,"context_line":"    RISC-V ecosystem."},{"line_number":299,"context_line":"  status: forming"},{"line_number":300,"context_line":"  url: https://etherpad.opendev.org/p/RISC-V-SIG"},{"line_number":301,"context_line":""},{"line_number":302,"context_line":"Resource Management:"},{"line_number":303,"context_line":"  chairs:"}],"source_content_type":"text/x-yaml","patch_set":2,"id":"a9ad1cfc_e5f939a6","line":300,"range":{"start_line":300,"start_character":7,"end_line":300,"end_character":48},"updated":"2026-06-17 21:29:59.000000000","message":"It would be nice if you can mention how one can contact everyone in the SIG, and what your immediate plans are in this etherpad. \n\nWe have heard from folks on the RISC-V foundation, and it would be very nice to make connections and collaborate on your work","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":28748,"name":"chenker","email":"chen.ke14@zte.com.cn","username":"chenke"},"change_message_id":"0bc7e0112555a26e3f32cab802d430324343e5e5","unresolved":false,"context_lines":[{"line_number":297,"context_line":"    open source projects, including OpenStack, and promoting the development of the "},{"line_number":298,"context_line":"    RISC-V ecosystem."},{"line_number":299,"context_line":"  status: forming"},{"line_number":300,"context_line":"  url: https://etherpad.opendev.org/p/RISC-V-SIG"},{"line_number":301,"context_line":""},{"line_number":302,"context_line":"Resource Management:"},{"line_number":303,"context_line":"  chairs:"}],"source_content_type":"text/x-yaml","patch_set":2,"id":"97e6333c_51ccb970","line":300,"range":{"start_line":300,"start_character":7,"end_line":300,"end_character":48},"in_reply_to":"4c342f58_3ffe7108","updated":"2026-07-06 09:05:25.000000000","message":"Done","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"20261167ba0a4fb62c090df0d360b6bd5914eee0","unresolved":true,"context_lines":[{"line_number":297,"context_line":"    open source projects, including OpenStack, and promoting the development of the "},{"line_number":298,"context_line":"    RISC-V ecosystem."},{"line_number":299,"context_line":"  status: forming"},{"line_number":300,"context_line":"  url: https://etherpad.opendev.org/p/RISC-V-SIG"},{"line_number":301,"context_line":""},{"line_number":302,"context_line":"Resource Management:"},{"line_number":303,"context_line":"  chairs:"}],"source_content_type":"text/x-yaml","patch_set":2,"id":"4c342f58_3ffe7108","line":300,"range":{"start_line":300,"start_character":7,"end_line":300,"end_character":48},"in_reply_to":"53a76017_9da7c53f","updated":"2026-06-26 05:43:11.000000000","message":"That\u0027s great. Thanks for adding the content to the etherpad. If folks would like to get in touch with you, they might do so on the etherpad.. but, would probably prefer emailing the openstack-discuss email list. Any concerns with this? or do you have a better suggestion on how to work together with someone that might be interested?","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":28748,"name":"chenker","email":"chen.ke14@zte.com.cn","username":"chenke"},"change_message_id":"480452b79c60f907a3379e5064d90030a10554db","unresolved":true,"context_lines":[{"line_number":297,"context_line":"    open source projects, including OpenStack, and promoting the development of the "},{"line_number":298,"context_line":"    RISC-V ecosystem."},{"line_number":299,"context_line":"  status: forming"},{"line_number":300,"context_line":"  url: https://etherpad.opendev.org/p/RISC-V-SIG"},{"line_number":301,"context_line":""},{"line_number":302,"context_line":"Resource Management:"},{"line_number":303,"context_line":"  chairs:"}],"source_content_type":"text/x-yaml","patch_set":2,"id":"53a76017_9da7c53f","line":300,"range":{"start_line":300,"start_character":7,"end_line":300,"end_character":48},"in_reply_to":"5fb8223f_5b6c3a97","updated":"2026-06-24 11:43:44.000000000","message":"OK, thanks . I will tee LiXiang to driver this.","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":13252,"name":"Dr. Jens Harbott","display_name":"Jens Harbott (frickler)","email":"frickler@offenerstapel.de","username":"jrosenboom"},"change_message_id":"8e3254d308f47e81ec4fe57a80d2a0fc64f72bb6","unresolved":true,"context_lines":[{"line_number":297,"context_line":"    open source projects, including OpenStack, and promoting the development of the "},{"line_number":298,"context_line":"    RISC-V ecosystem."},{"line_number":299,"context_line":"  status: forming"},{"line_number":300,"context_line":"  url: https://etherpad.opendev.org/p/RISC-V-SIG"},{"line_number":301,"context_line":""},{"line_number":302,"context_line":"Resource Management:"},{"line_number":303,"context_line":"  chairs:"}],"source_content_type":"text/x-yaml","patch_set":2,"id":"5fb8223f_5b6c3a97","line":300,"range":{"start_line":300,"start_character":7,"end_line":300,"end_character":48},"in_reply_to":"a9ad1cfc_e5f939a6","updated":"2026-06-24 10:50:54.000000000","message":"I agree, it would be great if this could become more than a marketing activity, for example by providing resources like testing hardware and/or also engineering power to adapt projects for this platform","commit_id":"6c15b50d1a315064263147d42e0d1c6086672d3b"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"de395ec4e2acf71a8921912b11ffd44264c66e4f","unresolved":true,"context_lines":[{"line_number":289,"context_line":"      email: zhu.junyi@zte.com.cn"},{"line_number":290,"context_line":"      working-language: English"},{"line_number":291,"context_line":"  scope: \u003e"},{"line_number":292,"context_line":"    RISC-V is a free and open instruction set architecture (ISA). In recent years,"},{"line_number":293,"context_line":"    a growing number of manufacturers have focused on the development of server-grade"},{"line_number":294,"context_line":"    RISC-V CPUs. This suggests that RISC-V may become a mainstream CPU architecture"},{"line_number":295,"context_line":"    for cloud infrastructure in the future, alongside X86 and ARM. This SIG is"}],"source_content_type":"text/x-yaml","patch_set":4,"id":"9317db1f_694146cf","line":292,"updated":"2026-06-23 21:41:50.000000000","message":"please wrap these lines at 79 characters if you make another patch","commit_id":"f26a9af6c4fae25ed2a40112511ddc66f5e4d412"},{"author":{"_account_id":28748,"name":"chenker","email":"chen.ke14@zte.com.cn","username":"chenke"},"change_message_id":"0bc7e0112555a26e3f32cab802d430324343e5e5","unresolved":false,"context_lines":[{"line_number":289,"context_line":"      email: zhu.junyi@zte.com.cn"},{"line_number":290,"context_line":"      working-language: English"},{"line_number":291,"context_line":"  scope: \u003e"},{"line_number":292,"context_line":"    RISC-V is a free and open instruction set architecture (ISA). In recent years,"},{"line_number":293,"context_line":"    a growing number of manufacturers have focused on the development of server-grade"},{"line_number":294,"context_line":"    RISC-V CPUs. This suggests that RISC-V may become a mainstream CPU architecture"},{"line_number":295,"context_line":"    for cloud infrastructure in the future, alongside X86 and ARM. This SIG is"}],"source_content_type":"text/x-yaml","patch_set":4,"id":"bc8a85cc_65853f70","line":292,"in_reply_to":"71b79abe_fde79414","updated":"2026-07-06 09:05:25.000000000","message":"Done","commit_id":"f26a9af6c4fae25ed2a40112511ddc66f5e4d412"},{"author":{"_account_id":28748,"name":"chenker","email":"chen.ke14@zte.com.cn","username":"chenke"},"change_message_id":"480452b79c60f907a3379e5064d90030a10554db","unresolved":true,"context_lines":[{"line_number":289,"context_line":"      email: zhu.junyi@zte.com.cn"},{"line_number":290,"context_line":"      working-language: English"},{"line_number":291,"context_line":"  scope: \u003e"},{"line_number":292,"context_line":"    RISC-V is a free and open instruction set architecture (ISA). In recent years,"},{"line_number":293,"context_line":"    a growing number of manufacturers have focused on the development of server-grade"},{"line_number":294,"context_line":"    RISC-V CPUs. This suggests that RISC-V may become a mainstream CPU architecture"},{"line_number":295,"context_line":"    for cloud infrastructure in the future, alongside X86 and ARM. This SIG is"}],"source_content_type":"text/x-yaml","patch_set":4,"id":"71b79abe_fde79414","line":292,"in_reply_to":"9317db1f_694146cf","updated":"2026-06-24 11:43:44.000000000","message":"ok, when make another patch, I will fix this.","commit_id":"f26a9af6c4fae25ed2a40112511ddc66f5e4d412"},{"author":{"_account_id":16643,"name":"Goutham Pacha Ravi","email":"gouthampravi@gmail.com","username":"gouthamr"},"change_message_id":"ce2ce04303ccbe047818aec870a063834127e3da","unresolved":true,"context_lines":[{"line_number":295,"context_line":"    open source projects, including OpenStack, and promoting the development of the"},{"line_number":296,"context_line":"    RISC-V ecosystem."},{"line_number":297,"context_line":"  status: forming"},{"line_number":298,"context_line":"  url: https://wiki.openstack.org/wiki/RISC-V-SIG"},{"line_number":299,"context_line":""},{"line_number":300,"context_line":"Resource Management:"},{"line_number":301,"context_line":"  chairs:"}],"source_content_type":"text/x-yaml","patch_set":8,"id":"0d4a6840_f45223d8","line":298,"range":{"start_line":298,"start_character":0,"end_line":298,"end_character":49},"updated":"2026-07-13 22:22:59.000000000","message":"I fixed up the formatting on this wiki. \nConsider the IRC channel, or setting up a meeting to attract more interest from the community","commit_id":"6dd9ea6057ee2a10bf66edfbbbc2a86d4e41315a"}]}