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{"/COMMIT_MSG":[{"author":{"_account_id":11655,"name":"Julia Kreger","email":"juliaashleykreger@gmail.com","username":"jkreger","status":"Flying to the moon with a Jetpack!"},"change_message_id":"be9ed6157bdf17aaf58433a5c424a896eafe78b1","unresolved":false,"context_lines":[{"line_number":7,"context_line":"Add support for Intel Speed Select in Ironic"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"Change-Id: Ic4c185ada78796a6df8c8bd4ae41281e628465e3"},{"line_number":10,"context_line":"Story: #2005390"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"3fce034c_cf26e117","line":10,"updated":"2019-04-10 20:26:54.000000000","message":"a Task will also be needed to close out the story. You\u0027ll want to create the tasks in advance and have one for the spec.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"}],"specs/approved/support-intel-speed-select.rst":[{"author":{"_account_id":11655,"name":"Julia Kreger","email":"juliaashleykreger@gmail.com","username":"jkreger","status":"Flying to the moon with a Jetpack!"},"change_message_id":"be9ed6157bdf17aaf58433a5c424a896eafe78b1","unresolved":false,"context_lines":[{"line_number":15,"context_line":"ownership(TCO)."},{"line_number":16,"context_line":"Intel® Speed Select Technology(SST) is a collection of features that improves"},{"line_number":17,"context_line":"performance and optimize TCO by providing more control over CPU performance."},{"line_number":18,"context_line":"With Intel® SST, one server can do more. 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One of the feature is"},{"line_number":19,"context_line":"Intel® Speed Select Technology-Performance Profile (SST-PP) allows configuring"},{"line_number":20,"context_line":"the CPU to run at 3 distinct operating points or profiles. It\u0027s supported on"},{"line_number":21,"context_line":"Intel processors[1]."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel® SST-PP, one can set the desired core count and their base and turbo"},{"line_number":24,"context_line":"frequency. It allows to set the number of cores and their frequencies which can"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_2fb685db","line":21,"range":{"start_line":20,"start_character":59,"end_line":21,"end_character":20},"updated":"2019-04-10 20:26:54.000000000","message":"This is a bit redundant...","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":17,"context_line":"performance and optimize TCO by providing more control over CPU performance."},{"line_number":18,"context_line":"With Intel® SST, one server can do more. One of the feature is"},{"line_number":19,"context_line":"Intel® Speed Select Technology-Performance Profile (SST-PP) allows configuring"},{"line_number":20,"context_line":"the CPU to run at 3 distinct operating points or profiles. It\u0027s supported on"},{"line_number":21,"context_line":"Intel processors[1]."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel® SST-PP, one can set the desired core count and their base and turbo"},{"line_number":24,"context_line":"frequency. It allows to set the number of cores and their frequencies which can"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_4ff5f4ca","line":21,"range":{"start_line":20,"start_character":59,"end_line":21,"end_character":20},"in_reply_to":"3fce034c_2fb685db","updated":"2019-04-15 16:11:10.000000000","message":"removed this.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":11655,"name":"Julia Kreger","email":"juliaashleykreger@gmail.com","username":"jkreger","status":"Flying to the moon with a Jetpack!"},"change_message_id":"be9ed6157bdf17aaf58433a5c424a896eafe78b1","unresolved":false,"context_lines":[{"line_number":20,"context_line":"the CPU to run at 3 distinct operating points or profiles. It\u0027s supported on"},{"line_number":21,"context_line":"Intel processors[1]."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel® SST-PP, one can set the desired core count and their base and turbo"},{"line_number":24,"context_line":"frequency. It allows to set the number of cores and their frequencies which can"},{"line_number":25,"context_line":"help to tune the server to specific workload performance."},{"line_number":26,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_4fdc3118","line":23,"range":{"start_line":23,"start_character":10,"end_line":23,"end_character":11},"updated":"2019-04-10 20:26:54.000000000","message":"Is the registered mark really required? We\u0027ve never... as far as I\u0027m aware, have had a vendor try to state that the text of their name is a registered mark in a document such as this.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":23851,"name":"Riccardo Pittau","email":"elfosardo@gmail.com","username":"elfosardo"},"change_message_id":"5a6655d39f2c748009c2d123bbf11620cf672868","unresolved":false,"context_lines":[{"line_number":20,"context_line":"the CPU to run at 3 distinct operating points or profiles. It\u0027s supported on"},{"line_number":21,"context_line":"Intel processors[1]."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel® SST-PP, one can set the desired core count and their base and turbo"},{"line_number":24,"context_line":"frequency. It allows to set the number of cores and their frequencies which can"},{"line_number":25,"context_line":"help to tune the server to specific workload performance."},{"line_number":26,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_c9ec96f5","line":23,"range":{"start_line":23,"start_character":10,"end_line":23,"end_character":11},"in_reply_to":"3fce034c_4fdc3118","updated":"2019-04-11 08:54:32.000000000","message":"++ was asking myself the same thing","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":20,"context_line":"the CPU to run at 3 distinct operating points or profiles. It\u0027s supported on"},{"line_number":21,"context_line":"Intel processors[1]."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel® SST-PP, one can set the desired core count and their base and turbo"},{"line_number":24,"context_line":"frequency. It allows to set the number of cores and their frequencies which can"},{"line_number":25,"context_line":"help to tune the server to specific workload performance."},{"line_number":26,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_8fe19c01","line":23,"range":{"start_line":23,"start_character":10,"end_line":23,"end_character":11},"in_reply_to":"3fce034c_4fdc3118","updated":"2019-04-15 16:11:10.000000000","message":"I have just kept one at the first mention and removed all other ones.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"43239bc18eff4ea7f0a2102485c1bd6ffc68853d","unresolved":false,"context_lines":[{"line_number":28,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":29,"context_line":"This spec proposes to support Intel® SST-PP feature in Ironic. This feature"},{"line_number":30,"context_line":"allows Ironic users to run higher performance baremetal instances with less"},{"line_number":31,"context_line":"TCO in their cloud."},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"Proposed change"},{"line_number":34,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_6905627a","line":31,"updated":"2019-04-11 09:03:18.000000000","message":"++ this should be phrased as a use case","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":11655,"name":"Julia Kreger","email":"juliaashleykreger@gmail.com","username":"jkreger","status":"Flying to the moon with a Jetpack!"},"change_message_id":"be9ed6157bdf17aaf58433a5c424a896eafe78b1","unresolved":false,"context_lines":[{"line_number":26,"context_line":""},{"line_number":27,"context_line":"Problem description"},{"line_number":28,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":29,"context_line":"This spec proposes to support Intel® SST-PP feature in Ironic. This feature"},{"line_number":30,"context_line":"allows Ironic users to run higher performance baremetal instances with less"},{"line_number":31,"context_line":"TCO in their cloud."},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"Proposed change"},{"line_number":34,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_2febe5b0","line":31,"range":{"start_line":29,"start_character":0,"end_line":31,"end_character":19},"updated":"2019-04-10 20:26:54.000000000","message":"What is the actual problem that this solves? This seems like a pure feature as opposed to fixing a problem that operators are expressing?","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":28,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":29,"context_line":"This spec proposes to support Intel® SST-PP feature in Ironic. This feature"},{"line_number":30,"context_line":"allows Ironic users to run higher performance baremetal instances with less"},{"line_number":31,"context_line":"TCO in their cloud."},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"Proposed change"},{"line_number":34,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_2f7d081c","line":31,"in_reply_to":"3fce034c_6905627a","updated":"2019-04-15 16:11:10.000000000","message":"Yes, this is feature support.\nI have rephrased as use case.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":23851,"name":"Riccardo Pittau","email":"elfosardo@gmail.com","username":"elfosardo"},"change_message_id":"5a6655d39f2c748009c2d123bbf11620cf672868","unresolved":false,"context_lines":[{"line_number":39,"context_line":"* 1 - Intel® SST-PP Config 1"},{"line_number":40,"context_line":"* 2 - Intel® SST-PP Config 2"},{"line_number":41,"context_line":""},{"line_number":42,"context_line":"Below table shows the list of actives cores and their base frequency at"},{"line_number":43,"context_line":"different SST-PP config levels::"},{"line_number":44,"context_line":""},{"line_number":45,"context_line":" ---------------------------------------------"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_a9010ab2","line":42,"range":{"start_line":42,"start_character":30,"end_line":42,"end_character":37},"updated":"2019-04-11 08:54:32.000000000","message":"nit: active","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":39,"context_line":"* 1 - Intel® SST-PP Config 1"},{"line_number":40,"context_line":"* 2 - Intel® SST-PP Config 2"},{"line_number":41,"context_line":""},{"line_number":42,"context_line":"Below table shows the list of actives cores and their base frequency at"},{"line_number":43,"context_line":"different SST-PP config levels::"},{"line_number":44,"context_line":""},{"line_number":45,"context_line":" ---------------------------------------------"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_cf1804d5","line":42,"range":{"start_line":42,"start_character":30,"end_line":42,"end_character":37},"in_reply_to":"3fce034c_a9010ab2","updated":"2019-04-15 16:11:10.000000000","message":"Done","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"43239bc18eff4ea7f0a2102485c1bd6ffc68853d","unresolved":false,"context_lines":[{"line_number":48,"context_line":" | Base        | 24      | 2.4               |"},{"line_number":49,"context_line":" | Config 1    | 20      | 2.5               |"},{"line_number":50,"context_line":" | Config 2    | 16      | 2.7               |"},{"line_number":51,"context_line":" ---------------------------------------------"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"Intel® SST-PP can be set over IPMI and Redfish. We will map these"},{"line_number":54,"context_line":"configurations to traits that Ironic understands."}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_890a0e88","line":51,"updated":"2019-04-11 09:03:18.000000000","message":"Everthing above this line is a part of the description, not a solution","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":48,"context_line":" | Base        | 24      | 2.4               |"},{"line_number":49,"context_line":" | Config 1    | 20      | 2.5               |"},{"line_number":50,"context_line":" | Config 2    | 16      | 2.7               |"},{"line_number":51,"context_line":" ---------------------------------------------"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"Intel® SST-PP can be set over IPMI and Redfish. We will map these"},{"line_number":54,"context_line":"configurations to traits that Ironic understands."}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_6f8230cb","line":51,"in_reply_to":"3fce034c_890a0e88","updated":"2019-04-15 16:11:10.000000000","message":"Moved it to problem description.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"43239bc18eff4ea7f0a2102485c1bd6ffc68853d","unresolved":false,"context_lines":[{"line_number":50,"context_line":" | Config 2    | 16      | 2.7               |"},{"line_number":51,"context_line":" ---------------------------------------------"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"Intel® SST-PP can be set over IPMI and Redfish. We will map these"},{"line_number":54,"context_line":"configurations to traits that Ironic understands."},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"* 0 - ``CUSTOM_INTEL_SPEED_SELECT_CONFIG_BASE``"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_29ff5a68","line":53,"updated":"2019-04-11 09:03:18.000000000","message":"Please provide some details.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":24828,"name":"Kaifeng Wang","email":"kaifeng.w@gmail.com","username":"wangkf"},"change_message_id":"8289ca89145a4a3bcc4041bf4bcff4e79f4d91fc","unresolved":false,"context_lines":[{"line_number":50,"context_line":" | Config 2    | 16      | 2.7               |"},{"line_number":51,"context_line":" ---------------------------------------------"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"Intel® SST-PP can be set over IPMI and Redfish. We will map these"},{"line_number":54,"context_line":"configurations to traits that Ironic understands."},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"* 0 - ``CUSTOM_INTEL_SPEED_SELECT_CONFIG_BASE``"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_29e67aea","line":53,"range":{"start_line":53,"start_character":35,"end_line":53,"end_character":38},"updated":"2019-04-11 09:26:57.000000000","message":"or?","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":50,"context_line":" | Config 2    | 16      | 2.7               |"},{"line_number":51,"context_line":" ---------------------------------------------"},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"Intel® SST-PP can be set over IPMI and Redfish. We will map these"},{"line_number":54,"context_line":"configurations to traits that Ironic understands."},{"line_number":55,"context_line":""},{"line_number":56,"context_line":"* 0 - ``CUSTOM_INTEL_SPEED_SELECT_CONFIG_BASE``"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_cf3564f9","line":53,"range":{"start_line":53,"start_character":35,"end_line":53,"end_character":38},"in_reply_to":"3fce034c_29e67aea","updated":"2019-04-15 16:11:10.000000000","message":"Done","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":24828,"name":"Kaifeng Wang","email":"kaifeng.w@gmail.com","username":"wangkf"},"change_message_id":"8289ca89145a4a3bcc4041bf4bcff4e79f4d91fc","unresolved":false,"context_lines":[{"line_number":77,"context_line":"    CUSTOM_INTEL_SPEED_SELECT_CONFIG_2"},{"line_number":78,"context_line":""},{"line_number":79,"context_line":".. NOTE: After ``ironic-inspector`` supports the discovery of Intel® SST-PP,"},{"line_number":80,"context_line":"  the manual step of updating the node\u0027s trait can be removed."},{"line_number":81,"context_line":""},{"line_number":82,"context_line":"Now, when user sends a request to boot a node with the ``baremetal`` flavor."},{"line_number":83,"context_line":"Placement API service will select the Ironic node that supports Intel® SST-PP."}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_69dc8218","line":80,"updated":"2019-04-11 09:26:57.000000000","message":"I feel we can remove this note, inspector is just one way of enrolling a node.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":77,"context_line":"    CUSTOM_INTEL_SPEED_SELECT_CONFIG_2"},{"line_number":78,"context_line":""},{"line_number":79,"context_line":".. NOTE: After ``ironic-inspector`` supports the discovery of Intel® SST-PP,"},{"line_number":80,"context_line":"  the manual step of updating the node\u0027s trait can be removed."},{"line_number":81,"context_line":""},{"line_number":82,"context_line":"Now, when user sends a request to boot a node with the ``baremetal`` flavor."},{"line_number":83,"context_line":"Placement API service will select the Ironic node that supports Intel® SST-PP."}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_4f2174b4","line":80,"in_reply_to":"3fce034c_69dc8218","updated":"2019-04-15 16:11:10.000000000","message":"Ok removed.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"43239bc18eff4ea7f0a2102485c1bd6ffc68853d","unresolved":false,"context_lines":[{"line_number":98,"context_line":"  updates the Ironic\u0027s node information with the trait. Ironic stores the"},{"line_number":99,"context_line":"  trait details in ``node.instance_info.traits``. Ironic will store a mapping"},{"line_number":100,"context_line":"  of the configuration level in trait and the raw code for IPMI in a new conf"},{"line_number":101,"context_line":"  parameter ``[deploy]/intel_speedselect_config``. The value will look like"},{"line_number":102,"context_line":"  this:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"  .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_4904267c","line":101,"updated":"2019-04-11 09:03:18.000000000","message":"I think it should be a new hardware type, descending from IPMIHardware with a new BIOSInterface that does this.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":11655,"name":"Julia Kreger","email":"juliaashleykreger@gmail.com","username":"jkreger","status":"Flying to the moon with a Jetpack!"},"change_message_id":"be9ed6157bdf17aaf58433a5c424a896eafe78b1","unresolved":false,"context_lines":[{"line_number":96,"context_line":"* Intel® SST-PP configuration level: This information is set by admins in the"},{"line_number":97,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"},{"line_number":98,"context_line":"  updates the Ironic\u0027s node information with the trait. Ironic stores the"},{"line_number":99,"context_line":"  trait details in ``node.instance_info.traits``. Ironic will store a mapping"},{"line_number":100,"context_line":"  of the configuration level in trait and the raw code for IPMI in a new conf"},{"line_number":101,"context_line":"  parameter ``[deploy]/intel_speedselect_config``. The value will look like"},{"line_number":102,"context_line":"  this:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"  .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_4fc67119","line":101,"range":{"start_line":99,"start_character":50,"end_line":101,"end_character":49},"updated":"2019-04-10 20:26:54.000000000","message":"So to trigger this by IPMI, it will need to be one or more raw commands?!? How will we even know what vendors support this through IPMI?","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":98,"context_line":"  updates the Ironic\u0027s node information with the trait. Ironic stores the"},{"line_number":99,"context_line":"  trait details in ``node.instance_info.traits``. Ironic will store a mapping"},{"line_number":100,"context_line":"  of the configuration level in trait and the raw code for IPMI in a new conf"},{"line_number":101,"context_line":"  parameter ``[deploy]/intel_speedselect_config``. The value will look like"},{"line_number":102,"context_line":"  this:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"  .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_161940d6","line":101,"in_reply_to":"3fce034c_4904267c","updated":"2019-04-15 16:11:10.000000000","message":"All the BIOS configuration is applied while cleaning.\nSST-PP should be applied while deployment.\n\nIs it ok to have a deploy_step in BIOS interface?","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":24828,"name":"Kaifeng Wang","email":"kaifeng.w@gmail.com","username":"wangkf"},"change_message_id":"8289ca89145a4a3bcc4041bf4bcff4e79f4d91fc","unresolved":false,"context_lines":[{"line_number":96,"context_line":"* Intel® SST-PP configuration level: This information is set by admins in the"},{"line_number":97,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"},{"line_number":98,"context_line":"  updates the Ironic\u0027s node information with the trait. Ironic stores the"},{"line_number":99,"context_line":"  trait details in ``node.instance_info.traits``. Ironic will store a mapping"},{"line_number":100,"context_line":"  of the configuration level in trait and the raw code for IPMI in a new conf"},{"line_number":101,"context_line":"  parameter ``[deploy]/intel_speedselect_config``. The value will look like"},{"line_number":102,"context_line":"  this:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"  .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_89cbee1c","line":101,"range":{"start_line":99,"start_character":50,"end_line":101,"end_character":49},"in_reply_to":"3fce034c_4fc67119","updated":"2019-04-11 09:26:57.000000000","message":"I am not sure whether the configuration of SST-PP is a standard feature supported by IPMI/Redfish? If not, how we know it works if the feature is maintained in the upstream but without real hardwares?\n\nI feel this mapping should be stored as arguments of deploy step template according to our roadmap.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":96,"context_line":"* Intel® SST-PP configuration level: This information is set by admins in the"},{"line_number":97,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"},{"line_number":98,"context_line":"  updates the Ironic\u0027s node information with the trait. Ironic stores the"},{"line_number":99,"context_line":"  trait details in ``node.instance_info.traits``. Ironic will store a mapping"},{"line_number":100,"context_line":"  of the configuration level in trait and the raw code for IPMI in a new conf"},{"line_number":101,"context_line":"  parameter ``[deploy]/intel_speedselect_config``. The value will look like"},{"line_number":102,"context_line":"  this:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"  .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_8a0d0a39","line":101,"range":{"start_line":99,"start_character":50,"end_line":101,"end_character":49},"in_reply_to":"3fce034c_4fc67119","updated":"2019-04-15 16:11:10.000000000","message":"It needs one IPMI command per socket. So total IPMI commands will be equal to no of sockets.\nIntel Server Boards support.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":11655,"name":"Julia Kreger","email":"juliaashleykreger@gmail.com","username":"jkreger","status":"Flying to the moon with a Jetpack!"},"change_message_id":"f67e59e9e93286aeeb9991e06f75dfc3f6eb37a0","unresolved":false,"context_lines":[{"line_number":96,"context_line":"* Intel® SST-PP configuration level: This information is set by admins in the"},{"line_number":97,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"},{"line_number":98,"context_line":"  updates the Ironic\u0027s node information with the trait. Ironic stores the"},{"line_number":99,"context_line":"  trait details in ``node.instance_info.traits``. Ironic will store a mapping"},{"line_number":100,"context_line":"  of the configuration level in trait and the raw code for IPMI in a new conf"},{"line_number":101,"context_line":"  parameter ``[deploy]/intel_speedselect_config``. The value will look like"},{"line_number":102,"context_line":"  this:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"  .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_8b918255","line":101,"range":{"start_line":99,"start_character":50,"end_line":101,"end_character":49},"in_reply_to":"3fce034c_89cbee1c","updated":"2019-04-12 19:20:30.000000000","message":"Dmitry ++\n\nI don\u0027t think we can really test it. We have some things we can\u0027t really test like the existing raw transport to ipmi, but still. :\\  Regardless, ++, a deploy template would be perfect.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":96,"context_line":"* Intel® SST-PP configuration level: This information is set by admins in the"},{"line_number":97,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"},{"line_number":98,"context_line":"  updates the Ironic\u0027s node information with the trait. Ironic stores the"},{"line_number":99,"context_line":"  trait details in ``node.instance_info.traits``. Ironic will store a mapping"},{"line_number":100,"context_line":"  of the configuration level in trait and the raw code for IPMI in a new conf"},{"line_number":101,"context_line":"  parameter ``[deploy]/intel_speedselect_config``. The value will look like"},{"line_number":102,"context_line":"  this:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"  .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_ae06b085","line":101,"range":{"start_line":99,"start_character":50,"end_line":101,"end_character":49},"in_reply_to":"3fce034c_89cbee1c","updated":"2019-04-15 16:11:10.000000000","message":"The configuration is not yet a standardize in IPMI. But a proposal to be supported in Redfish is being worked.\nI will look into deploy step template. Thanks!","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":24828,"name":"Kaifeng Wang","email":"kaifeng.w@gmail.com","username":"wangkf"},"change_message_id":"8289ca89145a4a3bcc4041bf4bcff4e79f4d91fc","unresolved":false,"context_lines":[{"line_number":109,"context_line":"                            \"CUSTOM_INTEL_SPEED_SELECT_CONFIG_2\": \"0x02\"},"},{"line_number":110,"context_line":"                   help\u003d_(\u0027Default Intel® SST-PP config and hexa value mapping.\u0027))"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"  We also store this mapping in Node\u0027s ``extra`` field. Priority of the value"},{"line_number":113,"context_line":"  stored with node will be higher than the default config value."},{"line_number":114,"context_line":""},{"line_number":115,"context_line":"* No. of socket: Setting Intel® SST-PP needs to be done for every socket. The"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_692a42e8","line":112,"range":{"start_line":112,"start_character":2,"end_line":112,"end_character":54},"updated":"2019-04-11 09:26:57.000000000","message":"I believe we have consensus that ironic doesn\u0027t touch the extra field.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":11655,"name":"Julia Kreger","email":"juliaashleykreger@gmail.com","username":"jkreger","status":"Flying to the moon with a Jetpack!"},"change_message_id":"f67e59e9e93286aeeb9991e06f75dfc3f6eb37a0","unresolved":false,"context_lines":[{"line_number":109,"context_line":"                            \"CUSTOM_INTEL_SPEED_SELECT_CONFIG_2\": \"0x02\"},"},{"line_number":110,"context_line":"                   help\u003d_(\u0027Default Intel® SST-PP config and hexa value mapping.\u0027))"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"  We also store this mapping in Node\u0027s ``extra`` field. Priority of the value"},{"line_number":113,"context_line":"  stored with node will be higher than the default config value."},{"line_number":114,"context_line":""},{"line_number":115,"context_line":"* No. of socket: Setting Intel® SST-PP needs to be done for every socket. The"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_eb892626","line":112,"range":{"start_line":112,"start_character":2,"end_line":112,"end_character":54},"in_reply_to":"3fce034c_692a42e8","updated":"2019-04-12 19:20:30.000000000","message":"Correct, we don\u0027t touch the extra field, we leave it alone for operators to use as needed.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":109,"context_line":"                            \"CUSTOM_INTEL_SPEED_SELECT_CONFIG_2\": \"0x02\"},"},{"line_number":110,"context_line":"                   help\u003d_(\u0027Default Intel® SST-PP config and hexa value mapping.\u0027))"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"  We also store this mapping in Node\u0027s ``extra`` field. Priority of the value"},{"line_number":113,"context_line":"  stored with node will be higher than the default config value."},{"line_number":114,"context_line":""},{"line_number":115,"context_line":"* No. of socket: Setting Intel® SST-PP needs to be done for every socket. The"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_44fdd238","line":112,"range":{"start_line":112,"start_character":2,"end_line":112,"end_character":54},"in_reply_to":"3fce034c_692a42e8","updated":"2019-04-15 16:11:10.000000000","message":"Is properties a better option for this then?","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"43239bc18eff4ea7f0a2102485c1bd6ffc68853d","unresolved":false,"context_lines":[{"line_number":114,"context_line":""},{"line_number":115,"context_line":"* No. of socket: Setting Intel® SST-PP needs to be done for every socket. The"},{"line_number":116,"context_line":"  users will have to store the no. of sockets in"},{"line_number":117,"context_line":"  ``node.properties.socket_count``."},{"line_number":118,"context_line":""},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"Alternatives"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_e9f8727d","line":117,"updated":"2019-04-11 09:03:18.000000000","message":"++","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":11655,"name":"Julia Kreger","email":"juliaashleykreger@gmail.com","username":"jkreger","status":"Flying to the moon with a Jetpack!"},"change_message_id":"be9ed6157bdf17aaf58433a5c424a896eafe78b1","unresolved":false,"context_lines":[{"line_number":114,"context_line":""},{"line_number":115,"context_line":"* No. of socket: Setting Intel® SST-PP needs to be done for every socket. The"},{"line_number":116,"context_line":"  users will have to store the no. of sockets in"},{"line_number":117,"context_line":"  ``node.properties.socket_count``."},{"line_number":118,"context_line":""},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"Alternatives"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_ef3abd32","line":117,"updated":"2019-04-10 20:26:54.000000000","message":"Why? Why can\u0027t the management interface determine this and act appropriately. This increases the overall difficulty and barrier to actual use.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":114,"context_line":""},{"line_number":115,"context_line":"* No. of socket: Setting Intel® SST-PP needs to be done for every socket. The"},{"line_number":116,"context_line":"  users will have to store the no. of sockets in"},{"line_number":117,"context_line":"  ``node.properties.socket_count``."},{"line_number":118,"context_line":""},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"Alternatives"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_24f52658","line":117,"in_reply_to":"3fce034c_ef3abd32","updated":"2019-04-15 16:11:10.000000000","message":"Ok I will implement this in code which will find the no of sockets and then apply iss on each of them. Thanks!","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"43239bc18eff4ea7f0a2102485c1bd6ffc68853d","unresolved":false,"context_lines":[{"line_number":161,"context_line":""},{"line_number":162,"context_line":"* Add a new deploy step ``do_configure_intel_speedselect`` to configure"},{"line_number":163,"context_line":"  Intel® SST-PP on the nodes. This step will be added to class"},{"line_number":164,"context_line":"  ``AgentDeploy``."},{"line_number":165,"context_line":""},{"line_number":166,"context_line":"   .. code-block:: python"},{"line_number":167,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_09f61e91","line":164,"updated":"2019-04-11 09:03:18.000000000","message":"Actually, this all feels like a new BIOS interface","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":11655,"name":"Julia Kreger","email":"juliaashleykreger@gmail.com","username":"jkreger","status":"Flying to the moon with a Jetpack!"},"change_message_id":"be9ed6157bdf17aaf58433a5c424a896eafe78b1","unresolved":false,"context_lines":[{"line_number":161,"context_line":""},{"line_number":162,"context_line":"* Add a new deploy step ``do_configure_intel_speedselect`` to configure"},{"line_number":163,"context_line":"  Intel® SST-PP on the nodes. This step will be added to class"},{"line_number":164,"context_line":"  ``AgentDeploy``."},{"line_number":165,"context_line":""},{"line_number":166,"context_line":"   .. code-block:: python"},{"line_number":167,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_afefd5ae","line":164,"range":{"start_line":164,"start_character":0,"end_line":164,"end_character":17},"updated":"2019-04-10 20:26:54.000000000","message":"Why a deploy interface when it requires a management interface method to be present?","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":24828,"name":"Kaifeng Wang","email":"kaifeng.w@gmail.com","username":"wangkf"},"change_message_id":"8289ca89145a4a3bcc4041bf4bcff4e79f4d91fc","unresolved":false,"context_lines":[{"line_number":161,"context_line":""},{"line_number":162,"context_line":"* Add a new deploy step ``do_configure_intel_speedselect`` to configure"},{"line_number":163,"context_line":"  Intel® SST-PP on the nodes. This step will be added to class"},{"line_number":164,"context_line":"  ``AgentDeploy``."},{"line_number":165,"context_line":""},{"line_number":166,"context_line":"   .. code-block:: python"},{"line_number":167,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_299e7a07","line":164,"range":{"start_line":164,"start_character":0,"end_line":164,"end_character":17},"in_reply_to":"3fce034c_afefd5ae","updated":"2019-04-11 09:26:57.000000000","message":"Probably a misleading of our current document :) this likely falls into a bios interface, but we still don\u0027t have the priority range defined.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":23851,"name":"Riccardo Pittau","email":"elfosardo@gmail.com","username":"elfosardo"},"change_message_id":"5a6655d39f2c748009c2d123bbf11620cf672868","unresolved":false,"context_lines":[{"line_number":173,"context_line":"               task.driver.management.set_intel_speedselect(task, iss_trait)"},{"line_number":174,"context_line":"           return None"},{"line_number":175,"context_line":""},{"line_number":176,"context_line":"* The code to set Intel® SST-PP will be implemented in the ``ipmitool``"},{"line_number":177,"context_line":"  driver. The support for configuring Intel® SST-PP will be added in the"},{"line_number":178,"context_line":"  management interface of ``ipmitool`` driver. Basically we send the raw hexa"},{"line_number":179,"context_line":"  code corresponding the requested config to the node and do a power recycle"},{"line_number":180,"context_line":"  to reflect the changes."},{"line_number":181,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_a9efcae7","line":178,"range":{"start_line":176,"start_character":2,"end_line":178,"end_character":46},"updated":"2019-04-11 08:54:32.000000000","message":"since SST-PP can be also set by Redfish, it would be great to see an implementation for the redfish driver.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":173,"context_line":"               task.driver.management.set_intel_speedselect(task, iss_trait)"},{"line_number":174,"context_line":"           return None"},{"line_number":175,"context_line":""},{"line_number":176,"context_line":"* The code to set Intel® SST-PP will be implemented in the ``ipmitool``"},{"line_number":177,"context_line":"  driver. The support for configuring Intel® SST-PP will be added in the"},{"line_number":178,"context_line":"  management interface of ``ipmitool`` driver. Basically we send the raw hexa"},{"line_number":179,"context_line":"  code corresponding the requested config to the node and do a power recycle"},{"line_number":180,"context_line":"  to reflect the changes."},{"line_number":181,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_96c21085","line":178,"range":{"start_line":176,"start_character":2,"end_line":178,"end_character":46},"in_reply_to":"3fce034c_a9efcae7","updated":"2019-04-15 16:11:10.000000000","message":"Yes, I will add it once the Redfish API is ready.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":11655,"name":"Julia Kreger","email":"juliaashleykreger@gmail.com","username":"jkreger","status":"Flying to the moon with a Jetpack!"},"change_message_id":"be9ed6157bdf17aaf58433a5c424a896eafe78b1","unresolved":false,"context_lines":[{"line_number":256,"context_line":""},{"line_number":257,"context_line":"* Unit tests"},{"line_number":258,"context_line":""},{"line_number":259,"context_line":"* Add support for testing Intel® SST-PP in virtual BMC for gate test."},{"line_number":260,"context_line":""},{"line_number":261,"context_line":"Upgrades and Backwards Compatibility"},{"line_number":262,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_4f13d1b9","line":259,"range":{"start_line":259,"start_character":0,"end_line":259,"end_character":69},"updated":"2019-04-10 20:26:54.000000000","message":"I think this is not really necessary. All things condsidered, this is a fairly minor feature compared to the integration testing we do in CI.","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"52397d25c03cd61eb7e9c0f3f27f877a4b89f470","unresolved":false,"context_lines":[{"line_number":256,"context_line":""},{"line_number":257,"context_line":"* Unit tests"},{"line_number":258,"context_line":""},{"line_number":259,"context_line":"* Add support for testing Intel® SST-PP in virtual BMC for gate test."},{"line_number":260,"context_line":""},{"line_number":261,"context_line":"Upgrades and Backwards Compatibility"},{"line_number":262,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":2,"id":"3fce034c_0ad7daef","line":259,"range":{"start_line":259,"start_character":0,"end_line":259,"end_character":69},"in_reply_to":"3fce034c_4f13d1b9","updated":"2019-04-15 16:11:10.000000000","message":"Ok I have removed it. Thanks!","commit_id":"aece6350950852f548b5c6c05edb21633b6475ec"},{"author":{"_account_id":23851,"name":"Riccardo Pittau","email":"elfosardo@gmail.com","username":"elfosardo"},"change_message_id":"13cab1b73d602b54e1d734e5206f78a22ff2e27d","unresolved":false,"context_lines":[{"line_number":41,"context_line":"* 1 - Intel SST-PP Config 1"},{"line_number":42,"context_line":"* 2 - Intel SST-PP Config 2"},{"line_number":43,"context_line":""},{"line_number":44,"context_line":"Below table shows the list of active cores and their base frequency at"},{"line_number":45,"context_line":"different SST-PP config levels::"},{"line_number":46,"context_line":""},{"line_number":47,"context_line":" ---------------------------------------------"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3fce034c_627685a7","line":44,"range":{"start_line":44,"start_character":0,"end_line":44,"end_character":5},"updated":"2019-04-16 14:11:56.000000000","message":"nit: s/Below/The following","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"2eea74ebecf830b400f276b29ac1c5f9de914d2e","unresolved":false,"context_lines":[{"line_number":41,"context_line":"* 1 - Intel SST-PP Config 1"},{"line_number":42,"context_line":"* 2 - Intel SST-PP Config 2"},{"line_number":43,"context_line":""},{"line_number":44,"context_line":"Below table shows the list of active cores and their base frequency at"},{"line_number":45,"context_line":"different SST-PP config levels::"},{"line_number":46,"context_line":""},{"line_number":47,"context_line":" ---------------------------------------------"}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_7f13695d","line":44,"range":{"start_line":44,"start_character":0,"end_line":44,"end_character":5},"in_reply_to":"3fce034c_627685a7","updated":"2019-04-26 08:01:40.000000000","message":"Done","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":23851,"name":"Riccardo Pittau","email":"elfosardo@gmail.com","username":"elfosardo"},"change_message_id":"13cab1b73d602b54e1d734e5206f78a22ff2e27d","unresolved":false,"context_lines":[{"line_number":59,"context_line":"own hexa raw code that server understands. Ironic sends this code to the server"},{"line_number":60,"context_line":"via IPMI to set the desired SST-PP level."},{"line_number":61,"context_line":""},{"line_number":62,"context_line":".. NOTE: The Redfish API for managing SST-PP is not yet ready to use."},{"line_number":63,"context_line":""},{"line_number":64,"context_line":"We will map these configurations to traits that Ironic understands."},{"line_number":65,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"3fce034c_22707da5","line":62,"range":{"start_line":62,"start_character":0,"end_line":62,"end_character":69},"updated":"2019-04-16 14:11:56.000000000","message":"thanks for specifying this :)","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"2eea74ebecf830b400f276b29ac1c5f9de914d2e","unresolved":false,"context_lines":[{"line_number":59,"context_line":"own hexa raw code that server understands. Ironic sends this code to the server"},{"line_number":60,"context_line":"via IPMI to set the desired SST-PP level."},{"line_number":61,"context_line":""},{"line_number":62,"context_line":".. NOTE: The Redfish API for managing SST-PP is not yet ready to use."},{"line_number":63,"context_line":""},{"line_number":64,"context_line":"We will map these configurations to traits that Ironic understands."},{"line_number":65,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_9f0e5d30","line":62,"range":{"start_line":62,"start_character":0,"end_line":62,"end_character":69},"in_reply_to":"3fce034c_22707da5","updated":"2019-04-26 08:01:40.000000000","message":":)","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"824bdd8d4fcd4484246ac9aba21ee9616d43c4a5","unresolved":false,"context_lines":[{"line_number":93,"context_line":"Provisioning"},{"line_number":94,"context_line":"------------"},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"The Intel SST-PP needs to be set via IPMI/Redfish before powering on the node"},{"line_number":97,"context_line":"in the process of provisioning. Ironic API service receives the desired"},{"line_number":98,"context_line":"configuration in ``node.instance_info.traits`` in the boot request. Ironic will"},{"line_number":99,"context_line":"then configure the Intel SST-PP configuration if any of the traits is found in"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3fce034c_4dd82e1d","line":96,"range":{"start_line":96,"start_character":41,"end_line":96,"end_character":49},"updated":"2019-04-18 11:04:59.000000000","message":"Let\u0027s not mention Redfish since as you say it\u0027s not ready.","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"2eea74ebecf830b400f276b29ac1c5f9de914d2e","unresolved":false,"context_lines":[{"line_number":93,"context_line":"Provisioning"},{"line_number":94,"context_line":"------------"},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"The Intel SST-PP needs to be set via IPMI/Redfish before powering on the node"},{"line_number":97,"context_line":"in the process of provisioning. Ironic API service receives the desired"},{"line_number":98,"context_line":"configuration in ``node.instance_info.traits`` in the boot request. Ironic will"},{"line_number":99,"context_line":"then configure the Intel SST-PP configuration if any of the traits is found in"}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_3f1df165","line":96,"range":{"start_line":96,"start_character":41,"end_line":96,"end_character":49},"in_reply_to":"3fce034c_4dd82e1d","updated":"2019-04-26 08:01:40.000000000","message":"Ok removed.","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"824bdd8d4fcd4484246ac9aba21ee9616d43c4a5","unresolved":false,"context_lines":[{"line_number":99,"context_line":"then configure the Intel SST-PP configuration if any of the traits is found in"},{"line_number":100,"context_line":"the ``Node`` object and then power on the node."},{"line_number":101,"context_line":""},{"line_number":102,"context_line":"Ironic will need below details to configure Intel SST-PP on the node:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"* Intel SST-PP configuration level: This information is set by admins in the"},{"line_number":105,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3fce034c_6d43aab0","line":102,"range":{"start_line":102,"start_character":0,"end_line":102,"end_character":69},"updated":"2019-04-18 11:04:59.000000000","message":"Which hardware interface is going to do it? It feels that this spec implicitly suggests a new hardware type IntelIPMIHardware, inheriting IPMIHardware and adding a new BIOSInterface implementation. But it\u0027s not mentioned.","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"5a7b89a072297a8ca42d0d2c4b11f2e35be27fd1","unresolved":false,"context_lines":[{"line_number":99,"context_line":"then configure the Intel SST-PP configuration if any of the traits is found in"},{"line_number":100,"context_line":"the ``Node`` object and then power on the node."},{"line_number":101,"context_line":""},{"line_number":102,"context_line":"Ironic will need below details to configure Intel SST-PP on the node:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"* Intel SST-PP configuration level: This information is set by admins in the"},{"line_number":105,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_9108a5d9","line":102,"range":{"start_line":102,"start_character":0,"end_line":102,"end_character":69},"in_reply_to":"3fce034c_6d43aab0","updated":"2019-04-25 09:10:07.000000000","message":"Hi Dmitry, thank you for the suggestion.\nIntel Speed Select is a technology that can run on any hardware with supporting CPU and BMC. \nSo do we still need to have a new IntelIPMIHardware?","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"2eea74ebecf830b400f276b29ac1c5f9de914d2e","unresolved":false,"context_lines":[{"line_number":99,"context_line":"then configure the Intel SST-PP configuration if any of the traits is found in"},{"line_number":100,"context_line":"the ``Node`` object and then power on the node."},{"line_number":101,"context_line":""},{"line_number":102,"context_line":"Ironic will need below details to configure Intel SST-PP on the node:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"* Intel SST-PP configuration level: This information is set by admins in the"},{"line_number":105,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_22671428","line":102,"range":{"start_line":102,"start_character":0,"end_line":102,"end_character":69},"in_reply_to":"ffb9cba7_7163b11b","updated":"2019-04-26 08:01:40.000000000","message":"Yes, right. I have introduced a new hardware type in the spec.","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"9a1f03087c1c7247caca910bee6eb40fd86cda9c","unresolved":false,"context_lines":[{"line_number":99,"context_line":"then configure the Intel SST-PP configuration if any of the traits is found in"},{"line_number":100,"context_line":"the ``Node`` object and then power on the node."},{"line_number":101,"context_line":""},{"line_number":102,"context_line":"Ironic will need below details to configure Intel SST-PP on the node:"},{"line_number":103,"context_line":""},{"line_number":104,"context_line":"* Intel SST-PP configuration level: This information is set by admins in the"},{"line_number":105,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_7163b11b","line":102,"range":{"start_line":102,"start_character":0,"end_line":102,"end_character":69},"in_reply_to":"ffb9cba7_9108a5d9","updated":"2019-04-25 09:50:55.000000000","message":"\u003e any hardware with supporting CPU and BMC\n\nis different from\n\n\u003e any IPMI compatible hardware\n\nright? That means it\u0027s a new hardware type.","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"824bdd8d4fcd4484246ac9aba21ee9616d43c4a5","unresolved":false,"context_lines":[{"line_number":104,"context_line":"* Intel SST-PP configuration level: This information is set by admins in the"},{"line_number":105,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"},{"line_number":106,"context_line":"  updates the Ironic\u0027s node information with the trait. Ironic stores the"},{"line_number":107,"context_line":"  trait details in ``node.instance_info.traits``. Ironic will store a mapping"},{"line_number":108,"context_line":"  of the configuration level in trait and the raw code for IPMI in a new conf"},{"line_number":109,"context_line":"  parameter ``[deploy]/intel_speedselect_config``. The value will look like"},{"line_number":110,"context_line":"  this:"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"  .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3fce034c_4df10e95","line":109,"range":{"start_line":107,"start_character":50,"end_line":109,"end_character":50},"updated":"2019-04-18 11:04:59.000000000","message":"Why do we need this option? This should be parameters for the clean or deploy step, not configuration options.","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"2eea74ebecf830b400f276b29ac1c5f9de914d2e","unresolved":false,"context_lines":[{"line_number":104,"context_line":"* Intel SST-PP configuration level: This information is set by admins in the"},{"line_number":105,"context_line":"  flavor\u0027s trait they want to boot the baremetal node with. Nova in turn"},{"line_number":106,"context_line":"  updates the Ironic\u0027s node information with the trait. Ironic stores the"},{"line_number":107,"context_line":"  trait details in ``node.instance_info.traits``. Ironic will store a mapping"},{"line_number":108,"context_line":"  of the configuration level in trait and the raw code for IPMI in a new conf"},{"line_number":109,"context_line":"  parameter ``[deploy]/intel_speedselect_config``. The value will look like"},{"line_number":110,"context_line":"  this:"},{"line_number":111,"context_line":""},{"line_number":112,"context_line":"  .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_c26dd804","line":109,"range":{"start_line":107,"start_character":50,"end_line":109,"end_character":50},"in_reply_to":"3fce034c_4df10e95","updated":"2019-04-26 08:01:40.000000000","message":"Removed and updated in the spec.","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"824bdd8d4fcd4484246ac9aba21ee9616d43c4a5","unresolved":false,"context_lines":[{"line_number":168,"context_line":"-----------------"},{"line_number":169,"context_line":""},{"line_number":170,"context_line":"* Add a new deploy step ``do_configure_intel_speedselect`` to configure"},{"line_number":171,"context_line":"  Intel SST-PP on the nodes. This step will be added to class"},{"line_number":172,"context_line":"  ``AgentDeploy``."},{"line_number":173,"context_line":""},{"line_number":174,"context_line":"   .. code-block:: python"},{"line_number":175,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"3fce034c_0d16a6a9","line":172,"range":{"start_line":171,"start_character":29,"end_line":172,"end_character":18},"updated":"2019-04-18 11:04:59.000000000","message":"It has to be added to a BIOS or Management interface of a specific hardware type.","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"2eea74ebecf830b400f276b29ac1c5f9de914d2e","unresolved":false,"context_lines":[{"line_number":168,"context_line":"-----------------"},{"line_number":169,"context_line":""},{"line_number":170,"context_line":"* Add a new deploy step ``do_configure_intel_speedselect`` to configure"},{"line_number":171,"context_line":"  Intel SST-PP on the nodes. This step will be added to class"},{"line_number":172,"context_line":"  ``AgentDeploy``."},{"line_number":173,"context_line":""},{"line_number":174,"context_line":"   .. code-block:: python"},{"line_number":175,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_e2701cdf","line":172,"range":{"start_line":171,"start_character":29,"end_line":172,"end_character":18},"in_reply_to":"3fce034c_0d16a6a9","updated":"2019-04-26 08:01:40.000000000","message":"Done","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"824bdd8d4fcd4484246ac9aba21ee9616d43c4a5","unresolved":false,"context_lines":[{"line_number":173,"context_line":""},{"line_number":174,"context_line":"   .. code-block:: python"},{"line_number":175,"context_line":""},{"line_number":176,"context_line":"       @base.deploy_step(priority\u003d200)"},{"line_number":177,"context_line":"       def do_configure_intel_speedselect(self, task):"},{"line_number":178,"context_line":"           traits\u003d task.node.instance_info.get(\u0027traits\u0027, [])"},{"line_number":179,"context_line":"           iss_trait \u003d manager_utils.get_intel_speedselect_trait(traits)"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3fce034c_8d2936e7","line":176,"range":{"start_line":176,"start_character":25,"end_line":176,"end_character":37},"updated":"2019-04-18 11:04:59.000000000","message":"missing a required argument for configuration level (instead of the configuration option).","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"2eea74ebecf830b400f276b29ac1c5f9de914d2e","unresolved":false,"context_lines":[{"line_number":173,"context_line":""},{"line_number":174,"context_line":"   .. code-block:: python"},{"line_number":175,"context_line":""},{"line_number":176,"context_line":"       @base.deploy_step(priority\u003d200)"},{"line_number":177,"context_line":"       def do_configure_intel_speedselect(self, task):"},{"line_number":178,"context_line":"           traits\u003d task.node.instance_info.get(\u0027traits\u0027, [])"},{"line_number":179,"context_line":"           iss_trait \u003d manager_utils.get_intel_speedselect_trait(traits)"}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_8277e0d4","line":176,"range":{"start_line":176,"start_character":25,"end_line":176,"end_character":37},"in_reply_to":"3fce034c_8d2936e7","updated":"2019-04-26 08:01:40.000000000","message":"Done","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"824bdd8d4fcd4484246ac9aba21ee9616d43c4a5","unresolved":false,"context_lines":[{"line_number":175,"context_line":""},{"line_number":176,"context_line":"       @base.deploy_step(priority\u003d200)"},{"line_number":177,"context_line":"       def do_configure_intel_speedselect(self, task):"},{"line_number":178,"context_line":"           traits\u003d task.node.instance_info.get(\u0027traits\u0027, [])"},{"line_number":179,"context_line":"           iss_trait \u003d manager_utils.get_intel_speedselect_trait(traits)"},{"line_number":180,"context_line":"           if iss_trait:"},{"line_number":181,"context_line":"               task.driver.management.set_intel_speedselect(task, iss_trait)"},{"line_number":182,"context_line":"           return None"},{"line_number":183,"context_line":""},{"line_number":184,"context_line":"* The code to set Intel SST-PP will be implemented in the ``ipmitool``"},{"line_number":185,"context_line":"  driver. The support for configuring Intel SST-PP will be added in the"}],"source_content_type":"text/x-rst","patch_set":3,"id":"3fce034c_ad267214","line":182,"range":{"start_line":178,"start_character":0,"end_line":182,"end_character":22},"updated":"2019-04-18 11:04:59.000000000","message":"nit: no need to provide the function body to avoid discussing it too early","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"2eea74ebecf830b400f276b29ac1c5f9de914d2e","unresolved":false,"context_lines":[{"line_number":175,"context_line":""},{"line_number":176,"context_line":"       @base.deploy_step(priority\u003d200)"},{"line_number":177,"context_line":"       def do_configure_intel_speedselect(self, task):"},{"line_number":178,"context_line":"           traits\u003d task.node.instance_info.get(\u0027traits\u0027, [])"},{"line_number":179,"context_line":"           iss_trait \u003d manager_utils.get_intel_speedselect_trait(traits)"},{"line_number":180,"context_line":"           if iss_trait:"},{"line_number":181,"context_line":"               task.driver.management.set_intel_speedselect(task, iss_trait)"},{"line_number":182,"context_line":"           return None"},{"line_number":183,"context_line":""},{"line_number":184,"context_line":"* The code to set Intel SST-PP will be implemented in the ``ipmitool``"},{"line_number":185,"context_line":"  driver. The support for configuring Intel SST-PP will be added in the"}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_a27224e2","line":182,"range":{"start_line":178,"start_character":0,"end_line":182,"end_character":22},"in_reply_to":"3fce034c_ad267214","updated":"2019-04-26 08:01:40.000000000","message":"Done","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"824bdd8d4fcd4484246ac9aba21ee9616d43c4a5","unresolved":false,"context_lines":[{"line_number":181,"context_line":"               task.driver.management.set_intel_speedselect(task, iss_trait)"},{"line_number":182,"context_line":"           return None"},{"line_number":183,"context_line":""},{"line_number":184,"context_line":"* The code to set Intel SST-PP will be implemented in the ``ipmitool``"},{"line_number":185,"context_line":"  driver. The support for configuring Intel SST-PP will be added in the"},{"line_number":186,"context_line":"  management interface of ``ipmitool`` driver. Basically we send the raw hexa"},{"line_number":187,"context_line":"  code corresponding the requested config to the node and do a power recycle"},{"line_number":188,"context_line":"  to reflect the changes."}],"source_content_type":"text/x-rst","patch_set":3,"id":"3fce034c_6d1c0ac1","line":185,"range":{"start_line":184,"start_character":2,"end_line":185,"end_character":9},"updated":"2019-04-18 11:04:59.000000000","message":"Since not everything managed by ipmitool supports Intel Speed Step, it has to be a new hardware type.","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"2eea74ebecf830b400f276b29ac1c5f9de914d2e","unresolved":false,"context_lines":[{"line_number":181,"context_line":"               task.driver.management.set_intel_speedselect(task, iss_trait)"},{"line_number":182,"context_line":"           return None"},{"line_number":183,"context_line":""},{"line_number":184,"context_line":"* The code to set Intel SST-PP will be implemented in the ``ipmitool``"},{"line_number":185,"context_line":"  driver. The support for configuring Intel SST-PP will be added in the"},{"line_number":186,"context_line":"  management interface of ``ipmitool`` driver. Basically we send the raw hexa"},{"line_number":187,"context_line":"  code corresponding the requested config to the node and do a power recycle"},{"line_number":188,"context_line":"  to reflect the changes."}],"source_content_type":"text/x-rst","patch_set":3,"id":"ffb9cba7_4281e88e","line":185,"range":{"start_line":184,"start_character":2,"end_line":185,"end_character":9},"in_reply_to":"3fce034c_6d1c0ac1","updated":"2019-04-26 08:01:40.000000000","message":"Done","commit_id":"b123a37fcb0352302adb53c51077411fe8aae754"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"114e8141ca35aa24b81593c8b21621ee85d3444f","unresolved":false,"context_lines":[{"line_number":95,"context_line":"in the process of provisioning. Ironic API service receives the desired"},{"line_number":96,"context_line":"configuration in ``node.instance_info.traits`` in the boot request. Ironic will"},{"line_number":97,"context_line":"then run the deploy template\u0027s step matching the trait. The deploy template"},{"line_number":98,"context_line":"will specify the new ``do_configure_intel_speedselect`` step which configure"},{"line_number":99,"context_line":"the Intel SST-PP configuration and then power on the node."},{"line_number":100,"context_line":""},{"line_number":101,"context_line":"Ironic will need below details to configure Intel SST-PP on the node:"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_91a710a8","line":98,"updated":"2019-04-29 04:04:09.000000000","message":"s/do_//","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"5e0bf111719db7c1ddd8da5f9e79d354e7421f5f","unresolved":false,"context_lines":[{"line_number":95,"context_line":"in the process of provisioning. Ironic API service receives the desired"},{"line_number":96,"context_line":"configuration in ``node.instance_info.traits`` in the boot request. Ironic will"},{"line_number":97,"context_line":"then run the deploy template\u0027s step matching the trait. The deploy template"},{"line_number":98,"context_line":"will specify the new ``do_configure_intel_speedselect`` step which configure"},{"line_number":99,"context_line":"the Intel SST-PP configuration and then power on the node."},{"line_number":100,"context_line":""},{"line_number":101,"context_line":"Ironic will need below details to configure Intel SST-PP on the node:"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_902ff83d","line":98,"in_reply_to":"ffb9cba7_91a710a8","updated":"2019-04-30 09:05:16.000000000","message":"Done","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":11076,"name":"Shivanand Tendulker","email":"stendulker@gmail.com","username":"stendulker"},"change_message_id":"4fff729d9b7acf107ffdd02869cc2d067033f985","unresolved":false,"context_lines":[{"line_number":176,"context_line":"                   ),"},{"line_number":177,"context_line":"                   \u0027required\u0027: True"},{"line_number":178,"context_line":"               },"},{"line_number":179,"context_line":"               \u0027socket_count\u0027: {"},{"line_number":180,"context_line":"                   \u0027description\u0027: ("},{"line_number":181,"context_line":"                       \"No. of sockets.\""},{"line_number":182,"context_line":"                   )"},{"line_number":183,"context_line":"               }"},{"line_number":184,"context_line":"           })"},{"line_number":185,"context_line":"           def do_configure_intel_speedselect(self, task, **kwargs):"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_e5ad5fe9","line":182,"range":{"start_line":179,"start_character":15,"end_line":182,"end_character":20},"updated":"2019-04-29 14:33:08.000000000","message":"This requires user to know the number of sockets on each bare metal. Can this be discovered at run time?","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"5e0bf111719db7c1ddd8da5f9e79d354e7421f5f","unresolved":false,"context_lines":[{"line_number":176,"context_line":"                   ),"},{"line_number":177,"context_line":"                   \u0027required\u0027: True"},{"line_number":178,"context_line":"               },"},{"line_number":179,"context_line":"               \u0027socket_count\u0027: {"},{"line_number":180,"context_line":"                   \u0027description\u0027: ("},{"line_number":181,"context_line":"                       \"No. of sockets.\""},{"line_number":182,"context_line":"                   )"},{"line_number":183,"context_line":"               }"},{"line_number":184,"context_line":"           })"},{"line_number":185,"context_line":"           def do_configure_intel_speedselect(self, task, **kwargs):"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_702a842c","line":182,"range":{"start_line":179,"start_character":15,"end_line":182,"end_character":20},"in_reply_to":"ffb9cba7_e5ad5fe9","updated":"2019-04-30 09:05:16.000000000","message":"Yes, this can be discovered. I added this as an optional parameter. If specified, don\u0027t look for it else discover it.","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"114e8141ca35aa24b81593c8b21621ee85d3444f","unresolved":false,"context_lines":[{"line_number":182,"context_line":"                   )"},{"line_number":183,"context_line":"               }"},{"line_number":184,"context_line":"           })"},{"line_number":185,"context_line":"           def do_configure_intel_speedselect(self, task, **kwargs):"},{"line_number":186,"context_line":"               return None"},{"line_number":187,"context_line":""},{"line_number":188,"context_line":"  Following is an example of the ``intel_speedselect_config`` value:"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_31bae4c0","line":185,"updated":"2019-04-29 04:04:09.000000000","message":"s/do_//","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"5e0bf111719db7c1ddd8da5f9e79d354e7421f5f","unresolved":false,"context_lines":[{"line_number":182,"context_line":"                   )"},{"line_number":183,"context_line":"               }"},{"line_number":184,"context_line":"           })"},{"line_number":185,"context_line":"           def do_configure_intel_speedselect(self, task, **kwargs):"},{"line_number":186,"context_line":"               return None"},{"line_number":187,"context_line":""},{"line_number":188,"context_line":"  Following is an example of the ``intel_speedselect_config`` value:"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_10230858","line":185,"in_reply_to":"ffb9cba7_31bae4c0","updated":"2019-04-30 09:05:16.000000000","message":"Done","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"114e8141ca35aa24b81593c8b21621ee85d3444f","unresolved":false,"context_lines":[{"line_number":191,"context_line":""},{"line_number":192,"context_line":"       {\"CUSTOM_INTEL_SPEED_SELECT_CONFIG_BASE\": \"0x00\","},{"line_number":193,"context_line":"        \"CUSTOM_INTEL_SPEED_SELECT_CONFIG_1\": \"0x01\","},{"line_number":194,"context_line":"        \"CUSTOM_INTEL_SPEED_SELECT_CONFIG_2\": \"0x02\"}"},{"line_number":195,"context_line":""},{"line_number":196,"context_line":""},{"line_number":197,"context_line":"Nova driver impact"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_51bf58af","line":194,"updated":"2019-04-29 04:04:09.000000000","message":"This doesn\u0027t look correct. I\u0027d expect three templates to be created, one witih intel_speedselect_config\u003d\"0x00\", the second with intel_speedselect_config\u003d\"0x01\", etc. Then it will work the way you described in \"scheduling\". Is it what you mean?","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":11076,"name":"Shivanand Tendulker","email":"stendulker@gmail.com","username":"stendulker"},"change_message_id":"4fff729d9b7acf107ffdd02869cc2d067033f985","unresolved":false,"context_lines":[{"line_number":191,"context_line":""},{"line_number":192,"context_line":"       {\"CUSTOM_INTEL_SPEED_SELECT_CONFIG_BASE\": \"0x00\","},{"line_number":193,"context_line":"        \"CUSTOM_INTEL_SPEED_SELECT_CONFIG_1\": \"0x01\","},{"line_number":194,"context_line":"        \"CUSTOM_INTEL_SPEED_SELECT_CONFIG_2\": \"0x02\"}"},{"line_number":195,"context_line":""},{"line_number":196,"context_line":""},{"line_number":197,"context_line":"Nova driver impact"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_e549df30","line":194,"in_reply_to":"ffb9cba7_51bf58af","updated":"2019-04-29 14:33:08.000000000","message":"+1","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"5e0bf111719db7c1ddd8da5f9e79d354e7421f5f","unresolved":false,"context_lines":[{"line_number":191,"context_line":""},{"line_number":192,"context_line":"       {\"CUSTOM_INTEL_SPEED_SELECT_CONFIG_BASE\": \"0x00\","},{"line_number":193,"context_line":"        \"CUSTOM_INTEL_SPEED_SELECT_CONFIG_1\": \"0x01\","},{"line_number":194,"context_line":"        \"CUSTOM_INTEL_SPEED_SELECT_CONFIG_2\": \"0x02\"}"},{"line_number":195,"context_line":""},{"line_number":196,"context_line":""},{"line_number":197,"context_line":"Nova driver impact"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_70dfe439","line":194,"in_reply_to":"ffb9cba7_51bf58af","updated":"2019-04-30 09:05:16.000000000","message":"Yes, I meant that only but I think it was confusing. I updated the spec to be more clear.","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"114e8141ca35aa24b81593c8b21621ee85d3444f","unresolved":false,"context_lines":[{"line_number":229,"context_line":"Other deployer impact"},{"line_number":230,"context_line":"---------------------"},{"line_number":231,"context_line":"Deployers wishing to use feature will have to update the ``socket_count``"},{"line_number":232,"context_line":"in Node properties and also add the Intel SST-PP configuration in Node"},{"line_number":233,"context_line":"traits."},{"line_number":234,"context_line":""},{"line_number":235,"context_line":".. NOTE: This will be automated with the support of ironic-inspector."}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_f1af6c7a","line":232,"updated":"2019-04-29 04:04:09.000000000","message":"This spec does not suggest adding socket_count to Node properties. Is it intended?","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":11076,"name":"Shivanand Tendulker","email":"stendulker@gmail.com","username":"stendulker"},"change_message_id":"4fff729d9b7acf107ffdd02869cc2d067033f985","unresolved":false,"context_lines":[{"line_number":229,"context_line":"Other deployer impact"},{"line_number":230,"context_line":"---------------------"},{"line_number":231,"context_line":"Deployers wishing to use feature will have to update the ``socket_count``"},{"line_number":232,"context_line":"in Node properties and also add the Intel SST-PP configuration in Node"},{"line_number":233,"context_line":"traits."},{"line_number":234,"context_line":""},{"line_number":235,"context_line":".. NOTE: This will be automated with the support of ironic-inspector."}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_05267369","line":232,"in_reply_to":"ffb9cba7_f1af6c7a","updated":"2019-04-29 14:33:08.000000000","message":"+1","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"5e0bf111719db7c1ddd8da5f9e79d354e7421f5f","unresolved":false,"context_lines":[{"line_number":229,"context_line":"Other deployer impact"},{"line_number":230,"context_line":"---------------------"},{"line_number":231,"context_line":"Deployers wishing to use feature will have to update the ``socket_count``"},{"line_number":232,"context_line":"in Node properties and also add the Intel SST-PP configuration in Node"},{"line_number":233,"context_line":"traits."},{"line_number":234,"context_line":""},{"line_number":235,"context_line":".. NOTE: This will be automated with the support of ironic-inspector."}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_f0719445","line":232,"in_reply_to":"ffb9cba7_f1af6c7a","updated":"2019-04-30 09:05:16.000000000","message":"Apologies, this was left from the last spec. I removed it.","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":11076,"name":"Shivanand Tendulker","email":"stendulker@gmail.com","username":"stendulker"},"change_message_id":"4fff729d9b7acf107ffdd02869cc2d067033f985","unresolved":false,"context_lines":[{"line_number":230,"context_line":"---------------------"},{"line_number":231,"context_line":"Deployers wishing to use feature will have to update the ``socket_count``"},{"line_number":232,"context_line":"in Node properties and also add the Intel SST-PP configuration in Node"},{"line_number":233,"context_line":"traits."},{"line_number":234,"context_line":""},{"line_number":235,"context_line":".. NOTE: This will be automated with the support of ironic-inspector."},{"line_number":236,"context_line":""}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_25b937e8","line":233,"range":{"start_line":233,"start_character":0,"end_line":233,"end_character":6},"updated":"2019-04-29 14:33:08.000000000","message":"They also need to create the corresponding deploy templates.","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"5e0bf111719db7c1ddd8da5f9e79d354e7421f5f","unresolved":false,"context_lines":[{"line_number":230,"context_line":"---------------------"},{"line_number":231,"context_line":"Deployers wishing to use feature will have to update the ``socket_count``"},{"line_number":232,"context_line":"in Node properties and also add the Intel SST-PP configuration in Node"},{"line_number":233,"context_line":"traits."},{"line_number":234,"context_line":""},{"line_number":235,"context_line":".. NOTE: This will be automated with the support of ironic-inspector."},{"line_number":236,"context_line":""}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_f0a674ab","line":233,"range":{"start_line":233,"start_character":0,"end_line":233,"end_character":6},"in_reply_to":"ffb9cba7_25b937e8","updated":"2019-04-30 09:05:16.000000000","message":"Done","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":11076,"name":"Shivanand Tendulker","email":"stendulker@gmail.com","username":"stendulker"},"change_message_id":"4fff729d9b7acf107ffdd02869cc2d067033f985","unresolved":false,"context_lines":[{"line_number":256,"context_line":""},{"line_number":257,"context_line":"* Write the test code."},{"line_number":258,"context_line":""},{"line_number":259,"context_line":"* Write a document explaining how to use Intel SST-PP."},{"line_number":260,"context_line":""},{"line_number":261,"context_line":""},{"line_number":262,"context_line":"Dependencies"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_458c6b35","line":259,"range":{"start_line":259,"start_character":1,"end_line":259,"end_character":54},"updated":"2019-04-29 14:33:08.000000000","message":"Do we need support third party CI for the new hardware type?","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"5e0bf111719db7c1ddd8da5f9e79d354e7421f5f","unresolved":false,"context_lines":[{"line_number":256,"context_line":""},{"line_number":257,"context_line":"* Write the test code."},{"line_number":258,"context_line":""},{"line_number":259,"context_line":"* Write a document explaining how to use Intel SST-PP."},{"line_number":260,"context_line":""},{"line_number":261,"context_line":""},{"line_number":262,"context_line":"Dependencies"}],"source_content_type":"text/x-rst","patch_set":4,"id":"ffb9cba7_10cd4865","line":259,"range":{"start_line":259,"start_character":1,"end_line":259,"end_character":54},"in_reply_to":"ffb9cba7_458c6b35","updated":"2019-04-30 09:05:16.000000000","message":"I am not sure. Julia suggested not to have one.\nPlease see her comment on PS2.","commit_id":"e8b75e863a7c839c64e4ff0251fbbb95eb2a5a99"},{"author":{"_account_id":11076,"name":"Shivanand Tendulker","email":"stendulker@gmail.com","username":"stendulker"},"change_message_id":"db97fc23a2cb2dc9566c85026719e931fad1f2ce","unresolved":false,"context_lines":[{"line_number":163,"context_line":"       class IntelIPMIHardware(IPMIHardware):"},{"line_number":164,"context_line":""},{"line_number":165,"context_line":"* Add a new management interface ``IntelIPMIManagement`` to manage configuring"},{"line_number":166,"context_line":"  Intel SST-PP on the servers. This class will have a new deploy step"},{"line_number":167,"context_line":"  ``configure_intel_speedselect`` to configure Intel SST-PP on the nodes."},{"line_number":168,"context_line":""},{"line_number":169,"context_line":"   .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":6,"id":"ffb9cba7_76efc0e8","line":166,"range":{"start_line":166,"start_character":52,"end_line":166,"end_character":69},"updated":"2019-05-02 12:33:36.000000000","message":"Will it be useful to have it as a clean step as well? One may want to toggle the configuration (to say \u0027base\u0027) while running cleaning.","commit_id":"fe7e5e4afcc592bae327a727d0f4a241e9303e31"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"7c9ec6c999b551c86b525212f1eef256bbe6da1e","unresolved":false,"context_lines":[{"line_number":163,"context_line":"       class IntelIPMIHardware(IPMIHardware):"},{"line_number":164,"context_line":""},{"line_number":165,"context_line":"* Add a new management interface ``IntelIPMIManagement`` to manage configuring"},{"line_number":166,"context_line":"  Intel SST-PP on the servers. This class will have a new deploy step"},{"line_number":167,"context_line":"  ``configure_intel_speedselect`` to configure Intel SST-PP on the nodes."},{"line_number":168,"context_line":""},{"line_number":169,"context_line":"   .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":6,"id":"dfbec78f_a6661f51","line":166,"range":{"start_line":166,"start_character":52,"end_line":166,"end_character":69},"in_reply_to":"dfbec78f_cc757fce","updated":"2019-05-03 08:26:18.000000000","message":"I added a note for it in the latest patch. Thanks!","commit_id":"fe7e5e4afcc592bae327a727d0f4a241e9303e31"},{"author":{"_account_id":11076,"name":"Shivanand Tendulker","email":"stendulker@gmail.com","username":"stendulker"},"change_message_id":"68f8d724015a1b6847c25a4b47c27f3dd7d727bb","unresolved":false,"context_lines":[{"line_number":163,"context_line":"       class IntelIPMIHardware(IPMIHardware):"},{"line_number":164,"context_line":""},{"line_number":165,"context_line":"* Add a new management interface ``IntelIPMIManagement`` to manage configuring"},{"line_number":166,"context_line":"  Intel SST-PP on the servers. This class will have a new deploy step"},{"line_number":167,"context_line":"  ``configure_intel_speedselect`` to configure Intel SST-PP on the nodes."},{"line_number":168,"context_line":""},{"line_number":169,"context_line":"   .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":6,"id":"dfbec78f_cc757fce","line":166,"range":{"start_line":166,"start_character":52,"end_line":166,"end_character":69},"in_reply_to":"dfbec78f_e90e3531","updated":"2019-05-02 16:33:46.000000000","message":"A step can be both deploy and clean based upon its use case.\nDeploy template related framework got added in Stein Release. All the steps added till Stein release are only \u0027clean steps\u0027. We would be enabling some of them as \u0027deploy steps\u0027 in Train. Ex: RAID configuration.","commit_id":"fe7e5e4afcc592bae327a727d0f4a241e9303e31"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"c313ed5ecf8cf9710cfa450aa6aa9ba39d6b6719","unresolved":false,"context_lines":[{"line_number":163,"context_line":"       class IntelIPMIHardware(IPMIHardware):"},{"line_number":164,"context_line":""},{"line_number":165,"context_line":"* Add a new management interface ``IntelIPMIManagement`` to manage configuring"},{"line_number":166,"context_line":"  Intel SST-PP on the servers. This class will have a new deploy step"},{"line_number":167,"context_line":"  ``configure_intel_speedselect`` to configure Intel SST-PP on the nodes."},{"line_number":168,"context_line":""},{"line_number":169,"context_line":"   .. code-block:: python"}],"source_content_type":"text/x-rst","patch_set":6,"id":"dfbec78f_e90e3531","line":166,"range":{"start_line":166,"start_character":52,"end_line":166,"end_character":69},"in_reply_to":"ffb9cba7_76efc0e8","updated":"2019-05-02 15:06:35.000000000","message":"I agree this is a useful use case.\nDo we have any step in ironic which is both deploy and clean step?\nAnd how do we define if the clean step should be run in automated cleaning?\nI think this one should be defined as clean step only for manual cleaning.","commit_id":"fe7e5e4afcc592bae327a727d0f4a241e9303e31"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":10,"context_line":""},{"line_number":11,"context_line":"https://storyboard.openstack.org/#!/story/2005390"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"Multiple type of servers are needed to handle diverse workloads. Purchasing"},{"line_number":14,"context_line":"and managing these servers introduces complexity and increases total cost of"},{"line_number":15,"context_line":"ownership(TCO)."},{"line_number":16,"context_line":"Intel Speed Select Technology(SST)[1] is a collection of features that improves"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_97bb06e4","line":13,"range":{"start_line":13,"start_character":9,"end_line":13,"end_character":13},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: types","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":10,"context_line":""},{"line_number":11,"context_line":"https://storyboard.openstack.org/#!/story/2005390"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"Multiple type of servers are needed to handle diverse workloads. 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One of the feature is Intel Speed Select"},{"line_number":20,"context_line":"Technology-Performance Profile (SST-PP) allows configuring the CPU to run at"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_177dd61b","line":17,"range":{"start_line":17,"start_character":16,"end_line":17,"end_character":24},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: optimizes","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":14,"context_line":"and managing these servers introduces complexity and increases total cost of"},{"line_number":15,"context_line":"ownership(TCO)."},{"line_number":16,"context_line":"Intel Speed Select Technology(SST)[1] is a collection of features that improves"},{"line_number":17,"context_line":"performance and optimize TCO by providing more control over CPU performance."},{"line_number":18,"context_line":"With Intel SST, one server can do more which means same server can be used to"},{"line_number":19,"context_line":"run different workloads. One of the feature is Intel Speed Select"},{"line_number":20,"context_line":"Technology-Performance Profile (SST-PP) allows configuring the CPU to run at"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_82f5e7cd","line":17,"range":{"start_line":17,"start_character":16,"end_line":17,"end_character":24},"in_reply_to":"dfbec78f_177dd61b","updated":"2019-05-06 08:44:50.000000000","message":"Done","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":15,"context_line":"ownership(TCO)."},{"line_number":16,"context_line":"Intel Speed Select Technology(SST)[1] is a collection of features that improves"},{"line_number":17,"context_line":"performance and optimize TCO by providing more control over CPU performance."},{"line_number":18,"context_line":"With Intel SST, one server can do more which means same server can be used to"},{"line_number":19,"context_line":"run different workloads. One of the feature is Intel Speed Select"},{"line_number":20,"context_line":"Technology-Performance Profile (SST-PP) allows configuring the CPU to run at"},{"line_number":21,"context_line":"3 distinct operating points or profiles."}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_b793aa4f","line":18,"range":{"start_line":18,"start_character":45,"end_line":18,"end_character":55},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: means the same","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":15,"context_line":"ownership(TCO)."},{"line_number":16,"context_line":"Intel Speed Select Technology(SST)[1] is a collection of features that improves"},{"line_number":17,"context_line":"performance and optimize TCO by providing more control over CPU performance."},{"line_number":18,"context_line":"With Intel SST, one server can do more which means same server can be used to"},{"line_number":19,"context_line":"run different workloads. One of the feature is Intel Speed Select"},{"line_number":20,"context_line":"Technology-Performance Profile (SST-PP) allows configuring the CPU to run at"},{"line_number":21,"context_line":"3 distinct operating points or profiles."}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_8224070f","line":18,"range":{"start_line":18,"start_character":45,"end_line":18,"end_character":55},"in_reply_to":"dfbec78f_b793aa4f","updated":"2019-05-06 08:44:50.000000000","message":"Done","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":17,"context_line":"performance and optimize TCO by providing more control over CPU performance."},{"line_number":18,"context_line":"With Intel SST, one server can do more which means same server can be used to"},{"line_number":19,"context_line":"run different workloads. One of the feature is Intel Speed Select"},{"line_number":20,"context_line":"Technology-Performance Profile (SST-PP) allows configuring the CPU to run at"},{"line_number":21,"context_line":"3 distinct operating points or profiles."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel SST-PP, one can set the desired core count and their base and turbo"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_97b786d9","line":20,"range":{"start_line":20,"start_character":39,"end_line":20,"end_character":46},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: which allows","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":17,"context_line":"performance and optimize TCO by providing more control over CPU performance."},{"line_number":18,"context_line":"With Intel SST, one server can do more which means same server can be used to"},{"line_number":19,"context_line":"run different workloads. One of the feature is Intel Speed Select"},{"line_number":20,"context_line":"Technology-Performance Profile (SST-PP) allows configuring the CPU to run at"},{"line_number":21,"context_line":"3 distinct operating points or profiles."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel SST-PP, one can set the desired core count and their base and turbo"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_e2a063a8","line":20,"range":{"start_line":20,"start_character":39,"end_line":20,"end_character":46},"in_reply_to":"dfbec78f_97b786d9","updated":"2019-05-06 08:44:50.000000000","message":"Done","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":21,"context_line":"3 distinct operating points or profiles."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel SST-PP, one can set the desired core count and their base and turbo"},{"line_number":24,"context_line":"frequency. It allows to set the number of cores and their frequencies which can"},{"line_number":25,"context_line":"help to tune the server to specific workload performance."},{"line_number":26,"context_line":""},{"line_number":27,"context_line":"Problem description"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_d7c41e43","line":24,"range":{"start_line":24,"start_character":0,"end_line":24,"end_character":9},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: frequencies","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":21,"context_line":"3 distinct operating points or profiles."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel SST-PP, one can set the desired core count and their base and turbo"},{"line_number":24,"context_line":"frequency. It allows to set the number of cores and their frequencies which can"},{"line_number":25,"context_line":"help to tune the server to specific workload performance."},{"line_number":26,"context_line":""},{"line_number":27,"context_line":"Problem description"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_22767b08","line":24,"range":{"start_line":24,"start_character":0,"end_line":24,"end_character":9},"in_reply_to":"dfbec78f_d7c41e43","updated":"2019-05-06 08:44:50.000000000","message":"Done","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":20,"context_line":"Technology-Performance Profile (SST-PP) allows configuring the CPU to run at"},{"line_number":21,"context_line":"3 distinct operating points or profiles."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel SST-PP, one can set the desired core count and their base and turbo"},{"line_number":24,"context_line":"frequency. It allows to set the number of cores and their frequencies which can"},{"line_number":25,"context_line":"help to tune the server to specific workload performance."},{"line_number":26,"context_line":""},{"line_number":27,"context_line":"Problem description"},{"line_number":28,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_17d076f7","line":25,"range":{"start_line":23,"start_character":0,"end_line":25,"end_character":57},"updated":"2019-05-03 16:17:01.000000000","message":"Isn\u0027t this twice the same?","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":20,"context_line":"Technology-Performance Profile (SST-PP) allows configuring the CPU to run at"},{"line_number":21,"context_line":"3 distinct operating points or profiles."},{"line_number":22,"context_line":""},{"line_number":23,"context_line":"With Intel SST-PP, one can set the desired core count and their base and turbo"},{"line_number":24,"context_line":"frequency. It allows to set the number of cores and their frequencies which can"},{"line_number":25,"context_line":"help to tune the server to specific workload performance."},{"line_number":26,"context_line":""},{"line_number":27,"context_line":"Problem description"},{"line_number":28,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_429b6f71","line":25,"range":{"start_line":23,"start_character":0,"end_line":25,"end_character":57},"in_reply_to":"dfbec78f_17d076f7","updated":"2019-05-06 08:44:50.000000000","message":"Right. I merged both the lines.","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":26,"context_line":""},{"line_number":27,"context_line":"Problem description"},{"line_number":28,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":29,"context_line":"This spec proposes to support Intel SST-PP feature in Ironic. With Intel"},{"line_number":30,"context_line":"SST-PP, Ironic users can:"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"* Run their servers at different configuration level."},{"line_number":33,"context_line":"* Each configuration level supports different number of active cores and"},{"line_number":34,"context_line":"  frequency."},{"line_number":35,"context_line":"* Same server can be used to run multiple different workloads thus decreasing"},{"line_number":36,"context_line":"  TCO."},{"line_number":37,"context_line":""},{"line_number":38,"context_line":"Intel SST-PP Speed Select supports three configuration levels:"},{"line_number":39,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_d7209efa","line":36,"range":{"start_line":29,"start_character":0,"end_line":36,"end_character":6},"updated":"2019-05-03 16:17:01.000000000","message":"This seems largely a repetition of the first paragraph. How about shrinking the first one down to something like:\n\"This spec proposes to add support for ... which is a collection of features to ...\" and explain the problems/use cases in this paragraph to avoid the duplication?","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":26,"context_line":""},{"line_number":27,"context_line":"Problem description"},{"line_number":28,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":29,"context_line":"This spec proposes to support Intel SST-PP feature in Ironic. With Intel"},{"line_number":30,"context_line":"SST-PP, Ironic users can:"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"* Run their servers at different configuration level."},{"line_number":33,"context_line":"* Each configuration level supports different number of active cores and"},{"line_number":34,"context_line":"  frequency."},{"line_number":35,"context_line":"* Same server can be used to run multiple different workloads thus decreasing"},{"line_number":36,"context_line":"  TCO."},{"line_number":37,"context_line":""},{"line_number":38,"context_line":"Intel SST-PP Speed Select supports three configuration levels:"},{"line_number":39,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_02949736","line":36,"range":{"start_line":29,"start_character":0,"end_line":36,"end_character":6},"in_reply_to":"dfbec78f_d7209efa","updated":"2019-05-06 08:44:50.000000000","message":"I didn\u0027t get your point here. I think the use cases listed are not repeated.","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":56,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":57,"context_line":""},{"line_number":58,"context_line":"Intel SST-PP can be set over IPMI. Each configuration level has its"},{"line_number":59,"context_line":"own hexa raw code that server understands. Ironic sends this code to the server"},{"line_number":60,"context_line":"via IPMI to set the desired SST-PP level."},{"line_number":61,"context_line":""},{"line_number":62,"context_line":"We will map these configurations to traits that Ironic understands."}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_7771b2e0","line":59,"range":{"start_line":59,"start_character":23,"end_line":59,"end_character":29},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: the server","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":56,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":57,"context_line":""},{"line_number":58,"context_line":"Intel SST-PP can be set over IPMI. Each configuration level has its"},{"line_number":59,"context_line":"own hexa raw code that server understands. Ironic sends this code to the server"},{"line_number":60,"context_line":"via IPMI to set the desired SST-PP level."},{"line_number":61,"context_line":""},{"line_number":62,"context_line":"We will map these configurations to traits that Ironic understands."}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_22ac3b8b","line":59,"range":{"start_line":59,"start_character":23,"end_line":59,"end_character":29},"in_reply_to":"dfbec78f_7771b2e0","updated":"2019-05-06 08:44:50.000000000","message":"Done","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10239,"name":"Dmitry Tantsur","email":"dtantsur@protonmail.com","username":"dtantsur"},"change_message_id":"0edba34ca1e89204e572c4fb82482822eaa2bbfa","unresolved":false,"context_lines":[{"line_number":80,"context_line":"Now, we also need to update the Ironic node\u0027s trait with the supported"},{"line_number":81,"context_line":"configuration levels."},{"line_number":82,"context_line":""},{"line_number":83,"context_line":"  $ openstack --os-baremetal-api-version 1.37 baremetal node add trait node-0 \\"},{"line_number":84,"context_line":"    CUSTOM_INTEL_SPEED_SELECT_CONFIG_BASE CUSTOM_INTEL_SPEED_SELECT_CONFIG_1 \\"},{"line_number":85,"context_line":"    CUSTOM_INTEL_SPEED_SELECT_CONFIG_2"},{"line_number":86,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_e0063621","line":83,"updated":"2019-05-03 18:15:23.000000000","message":"--os-baremetal-api-version is not needed","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":80,"context_line":"Now, we also need to update the Ironic node\u0027s trait with the supported"},{"line_number":81,"context_line":"configuration levels."},{"line_number":82,"context_line":""},{"line_number":83,"context_line":"  $ openstack --os-baremetal-api-version 1.37 baremetal node add trait node-0 \\"},{"line_number":84,"context_line":"    CUSTOM_INTEL_SPEED_SELECT_CONFIG_BASE CUSTOM_INTEL_SPEED_SELECT_CONFIG_1 \\"},{"line_number":85,"context_line":"    CUSTOM_INTEL_SPEED_SELECT_CONFIG_2"},{"line_number":86,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_1a697bbd","line":83,"range":{"start_line":83,"start_character":14,"end_line":83,"end_character":45},"updated":"2019-05-03 16:17:01.000000000","message":"Is this needed?","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":80,"context_line":"Now, we also need to update the Ironic node\u0027s trait with the supported"},{"line_number":81,"context_line":"configuration levels."},{"line_number":82,"context_line":""},{"line_number":83,"context_line":"  $ openstack --os-baremetal-api-version 1.37 baremetal node add trait node-0 \\"},{"line_number":84,"context_line":"    CUSTOM_INTEL_SPEED_SELECT_CONFIG_BASE CUSTOM_INTEL_SPEED_SELECT_CONFIG_1 \\"},{"line_number":85,"context_line":"    CUSTOM_INTEL_SPEED_SELECT_CONFIG_2"},{"line_number":86,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_42a92f79","line":83,"in_reply_to":"dfbec78f_e0063621","updated":"2019-05-06 08:44:50.000000000","message":"Done","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":85,"context_line":"    CUSTOM_INTEL_SPEED_SELECT_CONFIG_2"},{"line_number":86,"context_line":""},{"line_number":87,"context_line":""},{"line_number":88,"context_line":"Now, when user sends a request to boot a node with the ``baremetal`` flavor."},{"line_number":89,"context_line":"Placement API service will select the Ironic node that supports Intel SST-PP."},{"line_number":90,"context_line":""},{"line_number":91,"context_line":"Provisioning"},{"line_number":92,"context_line":"------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_573a6ee7","line":89,"range":{"start_line":88,"start_character":69,"end_line":89,"end_character":9},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: flavor, placement","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":85,"context_line":"    CUSTOM_INTEL_SPEED_SELECT_CONFIG_2"},{"line_number":86,"context_line":""},{"line_number":87,"context_line":""},{"line_number":88,"context_line":"Now, when user sends a request to boot a node with the ``baremetal`` flavor."},{"line_number":89,"context_line":"Placement API service will select the Ironic node that supports Intel SST-PP."},{"line_number":90,"context_line":""},{"line_number":91,"context_line":"Provisioning"},{"line_number":92,"context_line":"------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_c2b67fda","line":89,"range":{"start_line":88,"start_character":69,"end_line":89,"end_character":9},"in_reply_to":"dfbec78f_573a6ee7","updated":"2019-05-06 08:44:50.000000000","message":"Done","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":95,"context_line":"in the process of provisioning. Ironic API service receives the desired"},{"line_number":96,"context_line":"configuration in ``node.instance_info.traits`` in the boot request. Ironic will"},{"line_number":97,"context_line":"then run the deploy template\u0027s step matching the trait. The deploy template"},{"line_number":98,"context_line":"will specify the new ``configure_intel_speedselect`` step which configure"},{"line_number":99,"context_line":"the Intel SST-PP configuration and then power on the node."},{"line_number":100,"context_line":""},{"line_number":101,"context_line":"Ironic will need below details to configure Intel SST-PP on the node:"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_fa5fc70b","line":98,"range":{"start_line":98,"start_character":64,"end_line":98,"end_character":73},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: configures","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":95,"context_line":"in the process of provisioning. Ironic API service receives the desired"},{"line_number":96,"context_line":"configuration in ``node.instance_info.traits`` in the boot request. Ironic will"},{"line_number":97,"context_line":"then run the deploy template\u0027s step matching the trait. The deploy template"},{"line_number":98,"context_line":"will specify the new ``configure_intel_speedselect`` step which configure"},{"line_number":99,"context_line":"the Intel SST-PP configuration and then power on the node."},{"line_number":100,"context_line":""},{"line_number":101,"context_line":"Ironic will need below details to configure Intel SST-PP on the node:"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_e27863f9","line":98,"range":{"start_line":98,"start_character":64,"end_line":98,"end_character":73},"in_reply_to":"dfbec78f_fa5fc70b","updated":"2019-05-06 08:44:50.000000000","message":"Done","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":96,"context_line":"configuration in ``node.instance_info.traits`` in the boot request. Ironic will"},{"line_number":97,"context_line":"then run the deploy template\u0027s step matching the trait. The deploy template"},{"line_number":98,"context_line":"will specify the new ``configure_intel_speedselect`` step which configure"},{"line_number":99,"context_line":"the Intel SST-PP configuration and then power on the node."},{"line_number":100,"context_line":""},{"line_number":101,"context_line":"Ironic will need below details to configure Intel SST-PP on the node:"},{"line_number":102,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_7aa997dd","line":99,"range":{"start_line":99,"start_character":40,"end_line":99,"end_character":45},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: powers","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":96,"context_line":"configuration in ``node.instance_info.traits`` in the boot request. Ironic will"},{"line_number":97,"context_line":"then run the deploy template\u0027s step matching the trait. The deploy template"},{"line_number":98,"context_line":"will specify the new ``configure_intel_speedselect`` step which configure"},{"line_number":99,"context_line":"the Intel SST-PP configuration and then power on the node."},{"line_number":100,"context_line":""},{"line_number":101,"context_line":"Ironic will need below details to configure Intel SST-PP on the node:"},{"line_number":102,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_a2826bc7","line":99,"range":{"start_line":99,"start_character":40,"end_line":99,"end_character":45},"in_reply_to":"dfbec78f_7aa997dd","updated":"2019-05-06 08:44:50.000000000","message":"Done","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":105,"context_line":"  is set by admins in the  flavor\u0027s trait they want to boot the baremetal node"},{"line_number":106,"context_line":"  with. Nova in turn updates the Ironic\u0027s node information with the trait."},{"line_number":107,"context_line":""},{"line_number":108,"context_line":"* No. of socket: This is the no. of sockets per CPU. Setting Intel SST-PP needs"},{"line_number":109,"context_line":"  to be done for every socket."},{"line_number":110,"context_line":""},{"line_number":111,"context_line":"Both these information can be provided as an argument to the"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_dab7633a","line":108,"range":{"start_line":108,"start_character":2,"end_line":108,"end_character":15},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: Number of sockets","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":11292,"name":"Arne Wiebalck","email":"Arne.Wiebalck@cern.ch","username":"wiebalck"},"change_message_id":"1daef01949d48a1fe9054ba9cb850f5b4c44e7a9","unresolved":false,"context_lines":[{"line_number":105,"context_line":"  is set by admins in the  flavor\u0027s trait they want to boot the baremetal node"},{"line_number":106,"context_line":"  with. Nova in turn updates the Ironic\u0027s node information with the trait."},{"line_number":107,"context_line":""},{"line_number":108,"context_line":"* No. of socket: This is the no. of sockets per CPU. Setting Intel SST-PP needs"},{"line_number":109,"context_line":"  to be done for every socket."},{"line_number":110,"context_line":""},{"line_number":111,"context_line":"Both these information can be provided as an argument to the"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_9a832b57","line":108,"range":{"start_line":108,"start_character":29,"end_line":108,"end_character":32},"updated":"2019-05-03 16:17:01.000000000","message":"Nit: number","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":105,"context_line":"  is set by admins in the  flavor\u0027s trait they want to boot the baremetal node"},{"line_number":106,"context_line":"  with. Nova in turn updates the Ironic\u0027s node information with the trait."},{"line_number":107,"context_line":""},{"line_number":108,"context_line":"* No. of socket: This is the no. of sockets per CPU. Setting Intel SST-PP needs"},{"line_number":109,"context_line":"  to be done for every socket."},{"line_number":110,"context_line":""},{"line_number":111,"context_line":"Both these information can be provided as an argument to the"}],"source_content_type":"text/x-rst","patch_set":9,"id":"dfbec78f_c2875fd7","line":108,"range":{"start_line":108,"start_character":29,"end_line":108,"end_character":32},"in_reply_to":"dfbec78f_9a832b57","updated":"2019-05-06 08:44:50.000000000","message":"Done","commit_id":"c8214b7486266d4bb9a398321dfca06ff9026c4e"},{"author":{"_account_id":10206,"name":"Madhuri Kumari","email":"madhuri.kumari@intel.com","username":"Madhuri"},"change_message_id":"05de4c22d423e59b40207ec1fe18772788d4be62","unresolved":false,"context_lines":[{"line_number":105,"context_line":"  is set by admins in the  flavor\u0027s trait they want to boot the baremetal node"},{"line_number":106,"context_line":"  with. Nova in turn updates the Ironic\u0027s node information with the trait."},{"line_number":107,"context_line":""},{"line_number":108,"context_line":"* No. of socket: This is the no. of sockets per CPU. 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