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{"specs/newton/approved/xenapi-add-support-for-vgpu.rst":[{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"c76676ed4909dc96f5c3346490fa462958189095","unresolved":false,"context_lines":[{"line_number":40,"context_line":"[xenserver]"},{"line_number":41,"context_line":"..."},{"line_number":42,"context_line":"is_vgpu_enabled \u003d True"},{"line_number":43,"context_line":"vgpu_whitelist \u003d \u0027"},{"line_number":44,"context_line":"{\"vendor_id\": \"8086\","},{"line_number":45,"context_line":" \"product_id\": \"ffff\","},{"line_number":46,"context_line":" \"vgpu_type_id\": \"65496728-1ad1-4550-ae83-39a7785ba021\","}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_c9d1c0fd","line":43,"updated":"2016-02-15 14:32:34.000000000","message":"is_vgpu_enabled, sure, but is the vgpu_whitelist needed?  the PCI whitelist is clearly useful because not all PCI devices are candidates for passthrough - but the entire purpose of vGPU is to pass it through to a VM.\nIs this \u0027whitelist\u0027 actually a mapping from the PCI alias to a vGPU type?","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"52f922969a363716e771135678965c5a1af22996","unresolved":false,"context_lines":[{"line_number":40,"context_line":"[xenserver]"},{"line_number":41,"context_line":"..."},{"line_number":42,"context_line":"is_vgpu_enabled \u003d True"},{"line_number":43,"context_line":"vgpu_whitelist \u003d \u0027"},{"line_number":44,"context_line":"{\"vendor_id\": \"8086\","},{"line_number":45,"context_line":" \"product_id\": \"ffff\","},{"line_number":46,"context_line":" \"vgpu_type_id\": \"65496728-1ad1-4550-ae83-39a7785ba021\","}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_5f226b02","line":43,"in_reply_to":"dae33548_c9d1c0fd","updated":"2016-02-16 03:20:31.000000000","message":"yes, one of the purpose is the mapping between PCI alias and VGPU type. And one GPU group may support multiple VGPU models indeed but only single VGPU models can be configured for one GPU group. So this white list is needed.","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"c76676ed4909dc96f5c3346490fa462958189095","unresolved":false,"context_lines":[{"line_number":43,"context_line":"vgpu_whitelist \u003d \u0027"},{"line_number":44,"context_line":"{\"vendor_id\": \"8086\","},{"line_number":45,"context_line":" \"product_id\": \"ffff\","},{"line_number":46,"context_line":" \"vgpu_type_id\": \"65496728-1ad1-4550-ae83-39a7785ba021\","},{"line_number":47,"context_line":" \"gpu_group_id\": \"a2104733-846a-edcb-3170-a4ca2867d831\"}"},{"line_number":48,"context_line":"\u0027"},{"line_number":49,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_e99004ef","line":46,"updated":"2016-02-15 14:32:34.000000000","message":"We can\u0027t use UUIDs here; they are XAPI UUIDs and so would be a pain to obtain for every compute node.\nInstead we should either use the PCI ID of the PGPUs backing the gpu_group_id or a real name.","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"52f922969a363716e771135678965c5a1af22996","unresolved":false,"context_lines":[{"line_number":43,"context_line":"vgpu_whitelist \u003d \u0027"},{"line_number":44,"context_line":"{\"vendor_id\": \"8086\","},{"line_number":45,"context_line":" \"product_id\": \"ffff\","},{"line_number":46,"context_line":" \"vgpu_type_id\": \"65496728-1ad1-4550-ae83-39a7785ba021\","},{"line_number":47,"context_line":" \"gpu_group_id\": \"a2104733-846a-edcb-3170-a4ca2867d831\"}"},{"line_number":48,"context_line":"\u0027"},{"line_number":49,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_a2471c4a","line":46,"in_reply_to":"dae33548_e99004ef","updated":"2016-02-16 03:20:31.000000000","message":"Agree to not using UUID. But it seems we can\u0027t use PCI ID as one GPU group may contain multiple PGPUs and each PGPU has a PCI ID.","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"0ef5193d7897fe07952ab93e35fc9c2bddf7d39e","unresolved":false,"context_lines":[{"line_number":71,"context_line":"               \u0027for example: vgpu_whitelist \u003d \u0027"},{"line_number":72,"context_line":"               \u0027[{\"product_id\": \"ffff\",\u0027"},{"line_number":73,"context_line":"               \u0027  \"vendor_id\": \"8086\",\u0027"},{"line_number":74,"context_line":"               \u0027  \"vgpu_type_id\": \"a8f449e3-4a41-419a-9e26-1c9a8d20166a\", \u0027"},{"line_number":75,"context_line":"               \u0027  \"gpu_group_id\": \"a2104733-846a-edcb-3170-a4ca2867d831\",}]\u0027),"},{"line_number":76,"context_line":"    ]"},{"line_number":77,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_780fb2e1","line":74,"updated":"2016-02-15 08:48:02.000000000","message":"Is it better to use VGPU\u0027s model-name instead of vgpu_type_id? and make gpu_group_id to optional. Can leave gpu_group_id as None if it doesn\u0027t care about which gpu group the VGPU will be consumed from. It\u0027s allowed if it only support single VGPU model in one host.","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"c76676ed4909dc96f5c3346490fa462958189095","unresolved":false,"context_lines":[{"line_number":71,"context_line":"               \u0027for example: vgpu_whitelist \u003d \u0027"},{"line_number":72,"context_line":"               \u0027[{\"product_id\": \"ffff\",\u0027"},{"line_number":73,"context_line":"               \u0027  \"vendor_id\": \"8086\",\u0027"},{"line_number":74,"context_line":"               \u0027  \"vgpu_type_id\": \"a8f449e3-4a41-419a-9e26-1c9a8d20166a\", \u0027"},{"line_number":75,"context_line":"               \u0027  \"gpu_group_id\": \"a2104733-846a-edcb-3170-a4ca2867d831\",}]\u0027),"},{"line_number":76,"context_line":"    ]"},{"line_number":77,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_89b69888","line":74,"in_reply_to":"dae33548_780fb2e1","updated":"2016-02-15 14:32:34.000000000","message":"Yes; see above.","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":15648,"name":"Yingxin","email":"yingxin.cheng@intel.com","username":"Yingxin"},"change_message_id":"c9adae6cf83914bf647f57ecb558a008ac4e6fe0","unresolved":false,"context_lines":[{"line_number":77,"context_line":""},{"line_number":78,"context_line":"2. In _get_passthrough_devices(), add function to check the control flag of"},{"line_number":79,"context_line":"   \"is_vgpu_enabled\"; and generate the fake PCI list for those VGPU specified"},{"line_number":80,"context_line":"   in the option of vgpu_whitelist. Each available VGPU will has a single"},{"line_number":81,"context_line":"   fake PCI device. In order to distinguish these fake PCI devices from the"},{"line_number":82,"context_line":"   normal PCIs, we address them with a special domain ID (FFFF) and the"},{"line_number":83,"context_line":"   dev_id starts with a special prefix - \"vgpu_\"."}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_f3b9b316","line":80,"range":{"start_line":80,"start_character":20,"end_line":80,"end_character":34},"updated":"2016-02-17 08:37:06.000000000","message":"From the openstack user point-of-view, can the information for VGPU fake pci devices be automatically generated according to existing system information? So this whitelist of pci devices for VGPUs can be generated automatically, and the option \"pci_alias\" can also be generated on-the-fly. It could be difficult for openstack users to have the knowledge to configure those options, result in less users of this feature.\n\nSecondly, what will happen if is_vgpu_enabled is set to True but the underlying xenapi driver or xenserver doesn\u0027t support the feature. Should there be implemented a vgpu feature detection mechanism in the driver?","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"b87de0918b28dd681d646549f351bd48087f3b3c","unresolved":false,"context_lines":[{"line_number":77,"context_line":""},{"line_number":78,"context_line":"2. In _get_passthrough_devices(), add function to check the control flag of"},{"line_number":79,"context_line":"   \"is_vgpu_enabled\"; and generate the fake PCI list for those VGPU specified"},{"line_number":80,"context_line":"   in the option of vgpu_whitelist. Each available VGPU will has a single"},{"line_number":81,"context_line":"   fake PCI device. In order to distinguish these fake PCI devices from the"},{"line_number":82,"context_line":"   normal PCIs, we address them with a special domain ID (FFFF) and the"},{"line_number":83,"context_line":"   dev_id starts with a special prefix - \"vgpu_\"."}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_8137edfd","line":80,"range":{"start_line":80,"start_character":20,"end_line":80,"end_character":34},"in_reply_to":"dae33548_f3b9b316","updated":"2016-02-19 01:57:10.000000000","message":"I have pushed a new version spec in which it re-uses the PGPU\u0027s product_id and vendor_id. So we can use scripts to generate the pci whitelist and alis on-the-fly basing on PGPU\u0027s info except that the VGPU\u0027s model name should be supplied ahead. But I think it makes sense that the cloud admin should specify which VGPU should be enabled.\n\nFor the 2nd comment: Yes, at nova driver level it will check the host\u0027s capacity for VGPU. If it doesn\u0027t support VGPU, the fake PCI list will be empty. So even the control is true, it won\u0027t be used in the schedule phase.","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"c76676ed4909dc96f5c3346490fa462958189095","unresolved":false,"context_lines":[{"line_number":79,"context_line":"   \"is_vgpu_enabled\"; and generate the fake PCI list for those VGPU specified"},{"line_number":80,"context_line":"   in the option of vgpu_whitelist. Each available VGPU will has a single"},{"line_number":81,"context_line":"   fake PCI device. In order to distinguish these fake PCI devices from the"},{"line_number":82,"context_line":"   normal PCIs, we address them with a special domain ID (FFFF) and the"},{"line_number":83,"context_line":"   dev_id starts with a special prefix - \"vgpu_\"."},{"line_number":84,"context_line":""},{"line_number":85,"context_line":"3. Add new funtions in attach_pci_devices to invoke XenAPI to attach VGPU"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_29f30c75","line":82,"range":{"start_line":82,"start_character":58,"end_line":82,"end_character":62},"updated":"2016-02-15 14:32:34.000000000","message":"Is this the same FFFF as the product_id referenced several times above?  I assume not, but it\u0027s not clear.  Why is product_id FFFF?","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"52f922969a363716e771135678965c5a1af22996","unresolved":false,"context_lines":[{"line_number":79,"context_line":"   \"is_vgpu_enabled\"; and generate the fake PCI list for those VGPU specified"},{"line_number":80,"context_line":"   in the option of vgpu_whitelist. Each available VGPU will has a single"},{"line_number":81,"context_line":"   fake PCI device. In order to distinguish these fake PCI devices from the"},{"line_number":82,"context_line":"   normal PCIs, we address them with a special domain ID (FFFF) and the"},{"line_number":83,"context_line":"   dev_id starts with a special prefix - \"vgpu_\"."},{"line_number":84,"context_line":""},{"line_number":85,"context_line":"3. Add new funtions in attach_pci_devices to invoke XenAPI to attach VGPU"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_82e818e4","line":82,"range":{"start_line":82,"start_character":58,"end_line":82,"end_character":62},"in_reply_to":"dae33548_29f30c75","updated":"2016-02-16 03:20:31.000000000","message":"they are not the same. The PCI resource pool is identified by the combination of vendor_id and product_id. If the GPU group is composed of only a single type of PGPU and we don\u0027t support multiple VGPU models in one host, we can use PGPU\u0027s product_id. Otherwise, we need different product_id for each VGPU model to generate separate resource pool. So then we need a special product_id to avoid possible conflict with other devices.","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"16cc3a674ac7580d78751ac05f5df4c27a31ccd6","unresolved":false,"context_lines":[{"line_number":79,"context_line":"   \"is_vgpu_enabled\"; and generate the fake PCI list for those VGPU specified"},{"line_number":80,"context_line":"   in the option of vgpu_whitelist. Each available VGPU will has a single"},{"line_number":81,"context_line":"   fake PCI device. In order to distinguish these fake PCI devices from the"},{"line_number":82,"context_line":"   normal PCIs, we address them with a special domain ID (FFFF) and the"},{"line_number":83,"context_line":"   dev_id starts with a special prefix - \"vgpu_\"."},{"line_number":84,"context_line":""},{"line_number":85,"context_line":"3. Add new funtions in attach_pci_devices to invoke XenAPI to attach VGPU"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_c8351fdb","line":82,"range":{"start_line":82,"start_character":58,"end_line":82,"end_character":62},"in_reply_to":"dae33548_82e818e4","updated":"2016-02-16 04:46:19.000000000","message":"Ah, it seems we can\u0027t use PGPU\u0027s product_id, as its real PCI will mess up the fake PCI resource pool. It\u0027s possible to choose the real PCI when claim the PCI resource for VGPU.","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"c76676ed4909dc96f5c3346490fa462958189095","unresolved":false,"context_lines":[{"line_number":80,"context_line":"   in the option of vgpu_whitelist. Each available VGPU will has a single"},{"line_number":81,"context_line":"   fake PCI device. In order to distinguish these fake PCI devices from the"},{"line_number":82,"context_line":"   normal PCIs, we address them with a special domain ID (FFFF) and the"},{"line_number":83,"context_line":"   dev_id starts with a special prefix - \"vgpu_\"."},{"line_number":84,"context_line":""},{"line_number":85,"context_line":"3. Add new funtions in attach_pci_devices to invoke XenAPI to attach VGPU"},{"line_number":86,"context_line":"   to the instance if the PCI is a fake one for VGPU."}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_e97484fe","line":83,"updated":"2016-02-15 14:32:34.000000000","message":"We should have an example of how this looks as returned from the driver (so it\u0027s clear how it will seem different to a PCI device)","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"52f922969a363716e771135678965c5a1af22996","unresolved":false,"context_lines":[{"line_number":80,"context_line":"   in the option of vgpu_whitelist. Each available VGPU will has a single"},{"line_number":81,"context_line":"   fake PCI device. In order to distinguish these fake PCI devices from the"},{"line_number":82,"context_line":"   normal PCIs, we address them with a special domain ID (FFFF) and the"},{"line_number":83,"context_line":"   dev_id starts with a special prefix - \"vgpu_\"."},{"line_number":84,"context_line":""},{"line_number":85,"context_line":"3. Add new funtions in attach_pci_devices to invoke XenAPI to attach VGPU"},{"line_number":86,"context_line":"   to the instance if the PCI is a fake one for VGPU."}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_e2bda4d8","line":83,"in_reply_to":"dae33548_e97484fe","updated":"2016-02-16 03:20:31.000000000","message":"Agree. I will add that information in the next patch set.","commit_id":"4aea07df967aec05f0967e1b100bdbb435ae4b6e"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"1b40237eec3be7aad727fcf263cc2f16c020e8d5","unresolved":false,"context_lines":[{"line_number":71,"context_line":"[xenserver]"},{"line_number":72,"context_line":"..."},{"line_number":73,"context_line":"is_vgpu_enabled \u003d True"},{"line_number":74,"context_line":"vgpu_whitelist \u003d \u0027"},{"line_number":75,"context_line":"{\"vendor_id\": \"8086\","},{"line_number":76,"context_line":" \"product_id\": \"041a\","},{"line_number":77,"context_line":" \"model_name\": \"Intel GVT-g on Haswell P4700\","}],"source_content_type":"text/x-rst","patch_set":3,"id":"dae33548_70f87e4a","line":74,"updated":"2016-02-19 02:32:29.000000000","message":"Thanks for Yingxin. By considering his comments, we may set a default vgpu_whitelist which include all of the supported PGPUs and one VGPU model supported by each PGPU. the default white list can omit the gpu _group_name. So users can get the VGPU feature by default without any special operations on the host. Anyone is welcome for further comments.","commit_id":"36c52a1ab0ec0d5eb6bb83043c561f7d060e68bc"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"53284840410347a1a6f99d80892bb962067749b9","unresolved":false,"context_lines":[{"line_number":304,"context_line":""},{"line_number":305,"context_line":"* Unit tests."},{"line_number":306,"context_line":""},{"line_number":307,"context_line":"* Citrix XenServer CI."},{"line_number":308,"context_line":""},{"line_number":309,"context_line":"Documentation Impact"},{"line_number":310,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":6,"id":"fa0719c6_aa4a6d81","line":307,"updated":"2016-03-21 18:34:57.000000000","message":"The implication here is our CI will be testing VGPU in OS; we need to be confident that we can do that before claiming it in this spec.","commit_id":"174ed926010a54157e4ed25c2c7a4ab1306c5c97"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"279377591b4bc21e30f824e596dbaa8329565a1e","unresolved":false,"context_lines":[{"line_number":304,"context_line":""},{"line_number":305,"context_line":"* Unit tests."},{"line_number":306,"context_line":""},{"line_number":307,"context_line":"* Citrix XenServer CI."},{"line_number":308,"context_line":""},{"line_number":309,"context_line":"Documentation Impact"},{"line_number":310,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":6,"id":"fa0719c6_9dc04a7e","line":307,"in_reply_to":"fa0719c6_aa4a6d81","updated":"2016-03-23 03:25:38.000000000","message":"Thanks for the reminder. Yes, we have been attempting to find solutions to cover VGPU testing via CI, but we still have problems to support that at present. I will update this part accordingly.","commit_id":"174ed926010a54157e4ed25c2c7a4ab1306c5c97"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"2b9e7beffbfe8bb6ebe7114158e711465ad580d0","unresolved":false,"context_lines":[{"line_number":8,"context_line":"XenAPI: Add support for Virtual GPU (VGPU)"},{"line_number":9,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"Include the URL of your launchpad blueprint:"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"https://blueprints.launchpad.net/nova/+spec/xenapi-add-support-for-vgpu"},{"line_number":14,"context_line":""}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_511b07ca","line":11,"updated":"2016-05-11 10:46:58.000000000","message":"Nit: this line should be deleted","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":8,"context_line":"XenAPI: Add support for Virtual GPU (VGPU)"},{"line_number":9,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"Include the URL of your launchpad blueprint:"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"https://blueprints.launchpad.net/nova/+spec/xenapi-add-support-for-vgpu"},{"line_number":14,"context_line":""}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_e6b7a4f3","line":11,"in_reply_to":"dab17558_511b07ca","updated":"2016-05-12 10:31:12.000000000","message":"Will delete","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"fb5248ab823121e0d971e6edeb031f47a5b542f6","unresolved":false,"context_lines":[{"line_number":29,"context_line":"----------"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"Some VGPU capable graphics processor units can simulate multiple virtual GPUs"},{"line_number":32,"context_line":"on a single physical GPU(PGPU). Each GPU may support multiple types of VGPUs"},{"line_number":33,"context_line":"but the capacity for each VGPU type is different. By default on XenServer,"},{"line_number":34,"context_line":"the PGPU has an enabled VGPU type list. Each type (has different model name)"},{"line_number":35,"context_line":"is predefined with a fixed capabilities: e.g. a fixed amount of frame buff,"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_8b76a104","line":32,"range":{"start_line":32,"start_character":45,"end_line":32,"end_character":76},"updated":"2016-05-12 09:12:10.000000000","message":"Not understand what is \"VGPU types\"\n\nhere, do you means the type of VGPUs from the same GPU is different ? \n\nBut you mention the relation between VGPUs and GPU like SRIOV.\n\nso if all VGPU from same GPU, their type should be same.\n \n \nAs the follow example: \nGPU card type: Intel Corporation Xeon E3-1200 v3\n\none example of VGPU types is ”Intel GVT-g on Haswell P4700“， \n\nwhat other types may be?","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":29,"context_line":"----------"},{"line_number":30,"context_line":""},{"line_number":31,"context_line":"Some VGPU capable graphics processor units can simulate multiple virtual GPUs"},{"line_number":32,"context_line":"on a single physical GPU(PGPU). Each GPU may support multiple types of VGPUs"},{"line_number":33,"context_line":"but the capacity for each VGPU type is different. By default on XenServer,"},{"line_number":34,"context_line":"the PGPU has an enabled VGPU type list. Each type (has different model name)"},{"line_number":35,"context_line":"is predefined with a fixed capabilities: e.g. a fixed amount of frame buff,"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_66a61455","line":32,"range":{"start_line":32,"start_character":45,"end_line":32,"end_character":76},"in_reply_to":"dab17558_8b76a104","updated":"2016-05-12 10:31:12.000000000","message":"Some physical GPU supports different VGPU models. e.g. NVIDIA\nGRID K1 support K14OQ, K12OQ, K100.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"2b9e7beffbfe8bb6ebe7114158e711465ad580d0","unresolved":false,"context_lines":[{"line_number":55,"context_line":"each type of physical GPU(PGPU) has a pre-defined vendor ID and product ID."},{"line_number":56,"context_line":"By default, all the same type (same vendor ID and product ID) of PGPUs are"},{"line_number":57,"context_line":"managed in the same group. Once XenServer receives VGPU creation request,"},{"line_number":58,"context_line":"it will try to find an available PGPU from the specified group."},{"line_number":59,"context_line":""},{"line_number":60,"context_line":"With this feature, the users should be able to enable VGPU in VMs via"},{"line_number":61,"context_line":"passthrough PCI. Please see the following example:"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_11afbf2a","line":58,"updated":"2016-05-11 10:46:58.000000000","message":"nit: Its tempting to compare this to the SRIOV use case where there are virtual function pointers, etc. I see you do that further down, but it would help for the problem description too.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"2b9e7beffbfe8bb6ebe7114158e711465ad580d0","unresolved":false,"context_lines":[{"line_number":67,"context_line":"  the physical GPU PCI\u0027s vendor_id\u003d\"8086\", product_id\u003d\"041a\";"},{"line_number":68,"context_line":"  the supported VGPU model name is: \"VGPU 1\" and \"VGPU 2\""},{"line_number":69,"context_line":""},{"line_number":70,"context_line":"**Configuration for PCI passthrough:**"},{"line_number":71,"context_line":""},{"line_number":72,"context_line":"* nova.conf on the compute node::"},{"line_number":73,"context_line":""}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_9169effb","line":70,"updated":"2016-05-11 10:46:58.000000000","message":"Nit: This is the problem definition, it should not usually contain implementation details like these. Although its hard to describe this without this detail, so OK, I suppose.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"fb5248ab823121e0d971e6edeb031f47a5b542f6","unresolved":false,"context_lines":[{"line_number":90,"context_line":"* nova.conf on compute node::"},{"line_number":91,"context_line":""},{"line_number":92,"context_line":"  [xenserver]"},{"line_number":93,"context_line":"  is_vgpu_enabled \u003d True"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"**Configure flavor to specify the VGPU type and the count**"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_9abf1160","line":93,"range":{"start_line":93,"start_character":1,"end_line":93,"end_character":24},"updated":"2016-05-12 09:12:10.000000000","message":"Can you check the hypervisor capability whether it support vgpu, if it support, then the default vgpu is true.\n\nonly the cloud vendor do not want Nova to enable vgpu explicitly even the hypervisor support vgpu, then then set   \nis_vgpu_enabled as false.\n\n\nwe had better less conf for cloud vendor, this is friendly to them.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"2b9e7beffbfe8bb6ebe7114158e711465ad580d0","unresolved":false,"context_lines":[{"line_number":90,"context_line":"* nova.conf on compute node::"},{"line_number":91,"context_line":""},{"line_number":92,"context_line":"  [xenserver]"},{"line_number":93,"context_line":"  is_vgpu_enabled \u003d True"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"**Configure flavor to specify the VGPU type and the count**"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_d146d779","line":93,"updated":"2016-05-11 10:46:58.000000000","message":"Really? can we not enable this by default, and assume a zero passthrough whitelist to mean its not enabled?","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":90,"context_line":"* nova.conf on compute node::"},{"line_number":91,"context_line":""},{"line_number":92,"context_line":"  [xenserver]"},{"line_number":93,"context_line":"  is_vgpu_enabled \u003d True"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"**Configure flavor to specify the VGPU type and the count**"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_5d5d9e47","line":93,"range":{"start_line":93,"start_character":1,"end_line":93,"end_character":24},"in_reply_to":"dab17558_9abf1160","updated":"2016-05-12 10:31:12.000000000","message":"Agree with you. But see the above replying, I will remove this additional conf item and just depend on the whitelist.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":90,"context_line":"* nova.conf on compute node::"},{"line_number":91,"context_line":""},{"line_number":92,"context_line":"  [xenserver]"},{"line_number":93,"context_line":"  is_vgpu_enabled \u003d True"},{"line_number":94,"context_line":""},{"line_number":95,"context_line":""},{"line_number":96,"context_line":"**Configure flavor to specify the VGPU type and the count**"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_1ab31c0c","line":93,"in_reply_to":"dab17558_d146d779","updated":"2016-05-12 10:31:12.000000000","message":"Per this original design, I would like the whitelist to be automatically generated basing on the host\u0027 VGPU capability and the admin can enable/disable it simple via this conf item. The benefit is that it\u0027s easier for cloud admin to do configuration. But per our discussion recently, we will change to expose only one VGPU type or the physical GPU for each host. the admin need plan the whitelist before hand. So of course we can depend on whitelist.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"2b9e7beffbfe8bb6ebe7114158e711465ad580d0","unresolved":false,"context_lines":[{"line_number":132,"context_line":""},{"line_number":133,"context_line":"    cfg.StrOpt(\u0027is_vgpu_enabled\u0027,"},{"line_number":134,"context_line":"               default\u003dFalse,"},{"line_number":135,"context_line":"               help\u003d\u0027If the function of VGPU is enabled.\u0027)"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"* Add a new field - vf_model_name for PCI device to save the VGPU\u0027s"},{"line_number":138,"context_line":"  model name and add this field as the PCI pool\u0027s key; so that it"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_ac02d607","line":135,"updated":"2016-05-11 10:46:58.000000000","message":"why do we need this? why off by default?\n\nyou need to define flavors and whitelists before this can all activate anyways","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":132,"context_line":""},{"line_number":133,"context_line":"    cfg.StrOpt(\u0027is_vgpu_enabled\u0027,"},{"line_number":134,"context_line":"               default\u003dFalse,"},{"line_number":135,"context_line":"               help\u003d\u0027If the function of VGPU is enabled.\u0027)"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"* Add a new field - vf_model_name for PCI device to save the VGPU\u0027s"},{"line_number":138,"context_line":"  model name and add this field as the PCI pool\u0027s key; so that it"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_9d570626","line":135,"in_reply_to":"dab17558_ac02d607","updated":"2016-05-12 10:31:12.000000000","message":"Agree. Will remove this option.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"fb5248ab823121e0d971e6edeb031f47a5b542f6","unresolved":false,"context_lines":[{"line_number":176,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":177,"context_line":"        | address      | vendor_id | product_id |dev_type|vf_model_name|"},{"line_number":178,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":179,"context_line":"        | 0000:00:02.1 | 8086      |    041a    | Type-VF|   VGPU-1    |"},{"line_number":180,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":181,"context_line":"        | 0000:00:02.2 | 8086      |    041a    | Type-VF|   VGPU-1    |"},{"line_number":182,"context_line":"        +--------------+-----------+------------+--------+-------------+"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_809200f5","line":179,"range":{"start_line":179,"start_character":39,"end_line":179,"end_character":46},"updated":"2016-05-12 09:12:10.000000000","message":"for really sriov, the product_id is different with PF. \n\nsame vendor_id and product_id means same product.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":176,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":177,"context_line":"        | address      | vendor_id | product_id |dev_type|vf_model_name|"},{"line_number":178,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":179,"context_line":"        | 0000:00:02.1 | 8086      |    041a    | Type-VF|   VGPU-1    |"},{"line_number":180,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":181,"context_line":"        | 0000:00:02.2 | 8086      |    041a    | Type-VF|   VGPU-1    |"},{"line_number":182,"context_line":"        +--------------+-----------+------------+--------+-------------+"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_b077919e","line":179,"range":{"start_line":179,"start_character":39,"end_line":179,"end_character":46},"in_reply_to":"dab17558_809200f5","updated":"2016-05-12 10:31:12.000000000","message":"Understood. But VGPU at here is not a real PCI, there is no product_id. For faking PCI, just use the same as PF otherwise we don\u0027t know how to set the fake product_id and ensure no conflict. For VGPU, it will use vendor_id+product_id+vf_model_name to identify this device.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"fb5248ab823121e0d971e6edeb031f47a5b542f6","unresolved":false,"context_lines":[{"line_number":186,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":187,"context_line":"        | 0000:00:02.5 | 8086      |    041a    | Type-VF|   VGPU-2    |"},{"line_number":188,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":189,"context_line":"        | 0000:00:02.6 | 8086      |    041a    | Type-VF|   VGPU-2    |"},{"line_number":190,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"        The PCI pools are as:"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_e0b30ce8","line":189,"range":{"start_line":189,"start_character":9,"end_line":189,"end_character":23},"updated":"2016-05-12 09:12:10.000000000","message":"So are the fake address defined by the nova?  only nova know this fake address? \n\nAs I know the maximum of function number for a pci device is 8.\nif capacities bigger than 8, so it will be:\n 0000:00:02.8, 0000:00:02.9?","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":186,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":187,"context_line":"        | 0000:00:02.5 | 8086      |    041a    | Type-VF|   VGPU-2    |"},{"line_number":188,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":189,"context_line":"        | 0000:00:02.6 | 8086      |    041a    | Type-VF|   VGPU-2    |"},{"line_number":190,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"        The PCI pools are as:"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_708c0980","line":189,"range":{"start_line":189,"start_character":9,"end_line":189,"end_character":23},"in_reply_to":"dab17558_e0b30ce8","updated":"2016-05-12 10:31:12.000000000","message":"yes, only used internal to nova.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"2b9e7beffbfe8bb6ebe7114158e711465ad580d0","unresolved":false,"context_lines":[{"line_number":187,"context_line":"        | 0000:00:02.5 | 8086      |    041a    | Type-VF|   VGPU-2    |"},{"line_number":188,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":189,"context_line":"        | 0000:00:02.6 | 8086      |    041a    | Type-VF|   VGPU-2    |"},{"line_number":190,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"        The PCI pools are as:"},{"line_number":193,"context_line":"        +---------+----------+--------+---------------+---------+-----+"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_ac3ad696","line":190,"updated":"2016-05-11 10:46:58.000000000","message":"Doesn\u0027t this break down, because the use of VGPU-1 makes some of the other fake devices also get \"used\"?\n\nI know we have this issue when you passthrough a PF, and loose all the VFs, but I thought the current work around is to only expose one or the other to Nova, via the whitelist.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":187,"context_line":"        | 0000:00:02.5 | 8086      |    041a    | Type-VF|   VGPU-2    |"},{"line_number":188,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":189,"context_line":"        | 0000:00:02.6 | 8086      |    041a    | Type-VF|   VGPU-2    |"},{"line_number":190,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":191,"context_line":""},{"line_number":192,"context_line":"        The PCI pools are as:"},{"line_number":193,"context_line":"        +---------+----------+--------+---------------+---------+-----+"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_d0d17531","line":190,"in_reply_to":"dab17558_ac3ad696","updated":"2016-05-12 10:31:12.000000000","message":"Yes, to void the interaction between VGPUs on the same PGPU. We will change it to expose only one via the whitelist at the first phase.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"2b9e7beffbfe8bb6ebe7114158e711465ad580d0","unresolved":false,"context_lines":[{"line_number":195,"context_line":"        +---------+----------+--------+---------------+---------+-----+"},{"line_number":196,"context_line":"        | 8086    |   041a   |Type-PF |    None       |  None   | 1   |"},{"line_number":197,"context_line":"        +---------+----------+--------+---------------+---------+-----+"},{"line_number":198,"context_line":"        | 8086    |   041a   |Type-VF |   VGPU-1      |  None   | 2   |"},{"line_number":199,"context_line":"        +---------+----------+--------+---------------+---------+-----+"},{"line_number":200,"context_line":"        | 8086    |   041a   |Type-VF |   VGPU-2      |  None   | 4   |"},{"line_number":201,"context_line":"        +---------+----------+--------+---------------+---------+-----+"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_ac2f763d","line":198,"range":{"start_line":198,"start_character":22,"end_line":198,"end_character":26},"updated":"2016-05-11 10:46:58.000000000","message":"I guess its not possible to use product_id to encapsulate the vgpu_model_name? It feels like we have two types in this table now.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":195,"context_line":"        +---------+----------+--------+---------------+---------+-----+"},{"line_number":196,"context_line":"        | 8086    |   041a   |Type-PF |    None       |  None   | 1   |"},{"line_number":197,"context_line":"        +---------+----------+--------+---------------+---------+-----+"},{"line_number":198,"context_line":"        | 8086    |   041a   |Type-VF |   VGPU-1      |  None   | 2   |"},{"line_number":199,"context_line":"        +---------+----------+--------+---------------+---------+-----+"},{"line_number":200,"context_line":"        | 8086    |   041a   |Type-VF |   VGPU-2      |  None   | 4   |"},{"line_number":201,"context_line":"        +---------+----------+--------+---------------+---------+-----+"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_ae19ee24","line":198,"range":{"start_line":198,"start_character":22,"end_line":198,"end_character":26},"in_reply_to":"dab17558_ac2f763d","updated":"2016-05-12 10:31:12.000000000","message":"VGPU is identified by vendor_id+product_id+vgpu_model_name. But this problem will gone if we go to expose only one VGPU.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"2b9e7beffbfe8bb6ebe7114158e711465ad580d0","unresolved":false,"context_lines":[{"line_number":219,"context_line":"discussion, it\u0027s not worthy to do that as the relationship between PGPU"},{"line_number":220,"context_line":"and VGPU is very similar as the relationship between PF and VF in SRIOV"},{"line_number":221,"context_line":"PCI. The existing PCI logic can be re-used to handle similar things for"},{"line_number":222,"context_line":"VGPU. Further more, AMD\u0027s VPUG solution is basing on SR-IOV."},{"line_number":223,"context_line":""},{"line_number":224,"context_line":"Data model impact"},{"line_number":225,"context_line":"-----------------"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_ac6136ab","line":222,"updated":"2016-05-11 10:46:58.000000000","message":"I worry about my comment on line 190","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":219,"context_line":"discussion, it\u0027s not worthy to do that as the relationship between PGPU"},{"line_number":220,"context_line":"and VGPU is very similar as the relationship between PF and VF in SRIOV"},{"line_number":221,"context_line":"PCI. The existing PCI logic can be re-used to handle similar things for"},{"line_number":222,"context_line":"VGPU. Further more, AMD\u0027s VPUG solution is basing on SR-IOV."},{"line_number":223,"context_line":""},{"line_number":224,"context_line":"Data model impact"},{"line_number":225,"context_line":"-----------------"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_ceb9d2cd","line":222,"in_reply_to":"dab17558_ac6136ab","updated":"2016-05-12 10:31:12.000000000","message":"Done","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"fb5248ab823121e0d971e6edeb031f47a5b542f6","unresolved":false,"context_lines":[{"line_number":302,"context_line":"Testing"},{"line_number":303,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":304,"context_line":""},{"line_number":305,"context_line":"* Unit tests."},{"line_number":306,"context_line":""},{"line_number":307,"context_line":"Documentation Impact"},{"line_number":308,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_0b40f106","line":305,"range":{"start_line":305,"start_character":12,"end_line":305,"end_character":13},"updated":"2016-05-12 09:12:10.000000000","message":"Is unit tests enough?","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3bbddf8aa517e97abcddbe143b368093f0b168a8","unresolved":false,"context_lines":[{"line_number":302,"context_line":"Testing"},{"line_number":303,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":304,"context_line":""},{"line_number":305,"context_line":"* Unit tests."},{"line_number":306,"context_line":""},{"line_number":307,"context_line":"Documentation Impact"},{"line_number":308,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":7,"id":"dab17558_4e9fa250","line":305,"range":{"start_line":305,"start_character":12,"end_line":305,"end_character":13},"in_reply_to":"dab17558_0b40f106","updated":"2016-05-12 10:31:12.000000000","message":"VGPU test requires special test environment. We plan to set some nodepool to cover that for scenario test. But at the first phase, we will ensure unit tests ready firstly.","commit_id":"55c8ea400a5009875ca27111af9dfb3561ef7cee"},{"author":{"_account_id":12171,"name":"Moshe Levi","email":"moshele@nvidia.com","username":"moshele"},"change_message_id":"c90465e83336080ce8bb6b40f3ab88026417d1da","unresolved":false,"context_lines":[{"line_number":59,"context_line":"can host only one type of the VGPUs at the same time."},{"line_number":60,"context_line":""},{"line_number":61,"context_line":"Logically the relationship between PGPU and VGPU is very similar as the"},{"line_number":62,"context_line":"the relationship between PF and VF in SRIOV PCI, though VGPUs are not"},{"line_number":63,"context_line":"real PCI devices. So there is no PCI devices information reported from"},{"line_number":64,"context_line":"hypervisor."},{"line_number":65,"context_line":""}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_afdcd573","line":62,"range":{"start_line":62,"start_character":38,"end_line":62,"end_character":43},"updated":"2016-05-20 02:19:16.000000000","message":"s/SRIOV/SR-IOV","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"a5f4b19945f0ca0574720e9ef9b16cc426dd5124","unresolved":false,"context_lines":[{"line_number":59,"context_line":"can host only one type of the VGPUs at the same time."},{"line_number":60,"context_line":""},{"line_number":61,"context_line":"Logically the relationship between PGPU and VGPU is very similar as the"},{"line_number":62,"context_line":"the relationship between PF and VF in SRIOV PCI, though VGPUs are not"},{"line_number":63,"context_line":"real PCI devices. So there is no PCI devices information reported from"},{"line_number":64,"context_line":"hypervisor."},{"line_number":65,"context_line":""}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_479c2d0f","line":62,"range":{"start_line":62,"start_character":38,"end_line":62,"end_character":43},"in_reply_to":"bab6814e_afdcd573","updated":"2016-05-20 06:27:01.000000000","message":"Done","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":12171,"name":"Moshe Levi","email":"moshele@nvidia.com","username":"moshele"},"change_message_id":"c90465e83336080ce8bb6b40f3ab88026417d1da","unresolved":false,"context_lines":[{"line_number":68,"context_line":"passthrough SRIOV PCI."},{"line_number":69,"context_line":""},{"line_number":70,"context_line":""},{"line_number":71,"context_line":"Project Priority"},{"line_number":72,"context_line":"-----------------"},{"line_number":73,"context_line":""},{"line_number":74,"context_line":"None"},{"line_number":75,"context_line":""},{"line_number":76,"context_line":"Proposed change"},{"line_number":77,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_0f5401c8","line":74,"range":{"start_line":71,"start_character":0,"end_line":74,"end_character":4},"updated":"2016-05-20 02:19:16.000000000","message":"this can be remove it not part of newton template","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"a5f4b19945f0ca0574720e9ef9b16cc426dd5124","unresolved":false,"context_lines":[{"line_number":68,"context_line":"passthrough SRIOV PCI."},{"line_number":69,"context_line":""},{"line_number":70,"context_line":""},{"line_number":71,"context_line":"Project Priority"},{"line_number":72,"context_line":"-----------------"},{"line_number":73,"context_line":""},{"line_number":74,"context_line":"None"},{"line_number":75,"context_line":""},{"line_number":76,"context_line":"Proposed change"},{"line_number":77,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d"}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_a79d190c","line":74,"range":{"start_line":71,"start_character":0,"end_line":74,"end_character":4},"in_reply_to":"bab6814e_0f5401c8","updated":"2016-05-20 06:27:01.000000000","message":"Done","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":12171,"name":"Moshe Levi","email":"moshele@nvidia.com","username":"moshele"},"change_message_id":"c90465e83336080ce8bb6b40f3ab88026417d1da","unresolved":false,"context_lines":[{"line_number":96,"context_line":"time), we will retrict to enable only one type of VGPU for each PGPU."},{"line_number":97,"context_line":"We implement the restriction by adding up to one VGPU in the PCI"},{"line_number":98,"context_line":"white-list on compute node. The biggest benefit is that we can re-use"},{"line_number":99,"context_line":"the existing NOVA SRIOV PCI mechnism which supports PF and only one"},{"line_number":100,"context_line":"type VF; we needn\u0027t add logic to maintain the capacities for multiple"},{"line_number":101,"context_line":"types of VGPUs(consumming one VGPU will cause other VGPU type\u0027s"},{"line_number":102,"context_line":"capacity to be zero)."}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_0f0241b4","line":99,"range":{"start_line":99,"start_character":18,"end_line":99,"end_character":23},"updated":"2016-05-20 02:19:16.000000000","message":"s/SRIOV/SR-IOV","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"a5f4b19945f0ca0574720e9ef9b16cc426dd5124","unresolved":false,"context_lines":[{"line_number":96,"context_line":"time), we will retrict to enable only one type of VGPU for each PGPU."},{"line_number":97,"context_line":"We implement the restriction by adding up to one VGPU in the PCI"},{"line_number":98,"context_line":"white-list on compute node. The biggest benefit is that we can re-use"},{"line_number":99,"context_line":"the existing NOVA SRIOV PCI mechnism which supports PF and only one"},{"line_number":100,"context_line":"type VF; we needn\u0027t add logic to maintain the capacities for multiple"},{"line_number":101,"context_line":"types of VGPUs(consumming one VGPU will cause other VGPU type\u0027s"},{"line_number":102,"context_line":"capacity to be zero)."}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_c7881dc8","line":99,"range":{"start_line":99,"start_character":18,"end_line":99,"end_character":23},"in_reply_to":"bab6814e_0f0241b4","updated":"2016-05-20 06:27:01.000000000","message":"Done","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":12171,"name":"Moshe Levi","email":"moshele@nvidia.com","username":"moshele"},"change_message_id":"c90465e83336080ce8bb6b40f3ab88026417d1da","unresolved":false,"context_lines":[{"line_number":176,"context_line":""},{"line_number":177,"context_line":"  [DEFAULT]"},{"line_number":178,"context_line":"  pci_passthrough_whitelist\u003d\u0027["},{"line_number":179,"context_line":"  { \"vendor_id\":\"8086\",\"product_id\":\"041a\", \"vf_model_name\":\"VGPU 1\"}]\u0027"},{"line_number":180,"context_line":"  pci_alias\u003d\u0027{"},{"line_number":181,"context_line":"  \"name\":\"vgpu1\", \"vendor_id\":\"8086\", \"product_id\":\"041a\","},{"line_number":182,"context_line":"  \"vf_model_name\":\"VGPU 1\"}\u0027"}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_dab2b593","line":179,"range":{"start_line":179,"start_character":44,"end_line":179,"end_character":68},"updated":"2016-05-20 02:19:16.000000000","message":"why do you need the vf_model_name defined in the pci_passthrough_whitelist and in the pci_alias?\nis defining it in the pci_alias will be sufficient?","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"a5f4b19945f0ca0574720e9ef9b16cc426dd5124","unresolved":false,"context_lines":[{"line_number":176,"context_line":""},{"line_number":177,"context_line":"  [DEFAULT]"},{"line_number":178,"context_line":"  pci_passthrough_whitelist\u003d\u0027["},{"line_number":179,"context_line":"  { \"vendor_id\":\"8086\",\"product_id\":\"041a\", \"vf_model_name\":\"VGPU 1\"}]\u0027"},{"line_number":180,"context_line":"  pci_alias\u003d\u0027{"},{"line_number":181,"context_line":"  \"name\":\"vgpu1\", \"vendor_id\":\"8086\", \"product_id\":\"041a\","},{"line_number":182,"context_line":"  \"vf_model_name\":\"VGPU 1\"}\u0027"}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_0ac4ec5c","line":179,"range":{"start_line":179,"start_character":44,"end_line":179,"end_character":68},"in_reply_to":"bab6814e_dab2b593","updated":"2016-05-20 06:27:01.000000000","message":"refer to L97: there are multiple potential VGPU models/types on a single PGPU; so it depends on this model name from whitelist to know which specific VGPU model should be exposed.","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":12171,"name":"Moshe Levi","email":"moshele@nvidia.com","username":"moshele"},"change_message_id":"c90465e83336080ce8bb6b40f3ab88026417d1da","unresolved":false,"context_lines":[{"line_number":177,"context_line":"  [DEFAULT]"},{"line_number":178,"context_line":"  pci_passthrough_whitelist\u003d\u0027["},{"line_number":179,"context_line":"  { \"vendor_id\":\"8086\",\"product_id\":\"041a\", \"vf_model_name\":\"VGPU 1\"}]\u0027"},{"line_number":180,"context_line":"  pci_alias\u003d\u0027{"},{"line_number":181,"context_line":"  \"name\":\"vgpu1\", \"vendor_id\":\"8086\", \"product_id\":\"041a\","},{"line_number":182,"context_line":"  \"vf_model_name\":\"VGPU 1\"}\u0027"},{"line_number":183,"context_line":""},{"line_number":184,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":185,"context_line":""}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_0f9241f6","line":182,"range":{"start_line":180,"start_character":0,"end_line":182,"end_character":28},"updated":"2016-05-20 02:19:16.000000000","message":"pci_alias is currently read by  nova-api, and with my pci resize fix it will be read from nova-api and nova-compute \nsee https://review.openstack.org/#/c/307124/","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":12171,"name":"Moshe Levi","email":"moshele@nvidia.com","username":"moshele"},"change_message_id":"c90465e83336080ce8bb6b40f3ab88026417d1da","unresolved":false,"context_lines":[{"line_number":183,"context_line":""},{"line_number":184,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":185,"context_line":""},{"line_number":186,"context_line":"* nova flavor-key m1.medium set \"pci_passthrough:alias\"\u003d\"vgpu1\":\"1\""},{"line_number":187,"context_line":""},{"line_number":188,"context_line":"**Use the above flavor to boot VM**"},{"line_number":189,"context_line":""}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_2f67454e","line":186,"range":{"start_line":186,"start_character":56,"end_line":186,"end_character":67},"updated":"2016-05-20 02:19:16.000000000","message":"s/\"vgpu1\":\"1\"/\u0027vgpu1:1\"","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"a5f4b19945f0ca0574720e9ef9b16cc426dd5124","unresolved":false,"context_lines":[{"line_number":183,"context_line":""},{"line_number":184,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":185,"context_line":""},{"line_number":186,"context_line":"* nova flavor-key m1.medium set \"pci_passthrough:alias\"\u003d\"vgpu1\":\"1\""},{"line_number":187,"context_line":""},{"line_number":188,"context_line":"**Use the above flavor to boot VM**"},{"line_number":189,"context_line":""}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_e70e013a","line":186,"range":{"start_line":186,"start_character":56,"end_line":186,"end_character":67},"in_reply_to":"bab6814e_2f67454e","updated":"2016-05-20 06:27:01.000000000","message":"Done","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":12171,"name":"Moshe Levi","email":"moshele@nvidia.com","username":"moshele"},"change_message_id":"c90465e83336080ce8bb6b40f3ab88026417d1da","unresolved":false,"context_lines":[{"line_number":260,"context_line":"*  Control if the VGPU feature is enabled;"},{"line_number":261,"context_line":""},{"line_number":262,"context_line":"*  Add a new field - vf_model_name for PCI device and add it as the PCI"},{"line_number":263,"context_line":"   pool\u0027 key."},{"line_number":264,"context_line":""},{"line_number":265,"context_line":"*  Extend _ALIAS_SCHEMA and devspec to add process on vf_model_name."},{"line_number":266,"context_line":""}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_7a38e93d","line":263,"range":{"start_line":263,"start_character":7,"end_line":263,"end_character":8},"updated":"2016-05-20 02:19:16.000000000","message":"can be removed?","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"a5f4b19945f0ca0574720e9ef9b16cc426dd5124","unresolved":false,"context_lines":[{"line_number":260,"context_line":"*  Control if the VGPU feature is enabled;"},{"line_number":261,"context_line":""},{"line_number":262,"context_line":"*  Add a new field - vf_model_name for PCI device and add it as the PCI"},{"line_number":263,"context_line":"   pool\u0027 key."},{"line_number":264,"context_line":""},{"line_number":265,"context_line":"*  Extend _ALIAS_SCHEMA and devspec to add process on vf_model_name."},{"line_number":266,"context_line":""}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_c05da348","line":263,"range":{"start_line":263,"start_character":7,"end_line":263,"end_character":8},"in_reply_to":"bab6814e_7a38e93d","updated":"2016-05-20 06:27:01.000000000","message":"Yes, we can remove it. This field is for supporting multiple potential models in a single host. But we won\u0027t support that at current phase.","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":12171,"name":"Moshe Levi","email":"moshele@nvidia.com","username":"moshele"},"change_message_id":"c90465e83336080ce8bb6b40f3ab88026417d1da","unresolved":false,"context_lines":[{"line_number":265,"context_line":"*  Extend _ALIAS_SCHEMA and devspec to add process on vf_model_name."},{"line_number":266,"context_line":""},{"line_number":267,"context_line":"*  Create fake PCI devices basing on the capacity for the VGPU models and"},{"line_number":268,"context_line":"   upate the PCI\u0027s status basing on the VGPU assignment and the remaining"},{"line_number":269,"context_line":"   capacity."},{"line_number":270,"context_line":""},{"line_number":271,"context_line":"*  Create requested VGPU when spawn an instance which include a pass-through"}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_7a0f4988","line":268,"range":{"start_line":268,"start_character":3,"end_line":268,"end_character":8},"updated":"2016-05-20 02:19:16.000000000","message":"s/upate/update","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"a5f4b19945f0ca0574720e9ef9b16cc426dd5124","unresolved":false,"context_lines":[{"line_number":265,"context_line":"*  Extend _ALIAS_SCHEMA and devspec to add process on vf_model_name."},{"line_number":266,"context_line":""},{"line_number":267,"context_line":"*  Create fake PCI devices basing on the capacity for the VGPU models and"},{"line_number":268,"context_line":"   upate the PCI\u0027s status basing on the VGPU assignment and the remaining"},{"line_number":269,"context_line":"   capacity."},{"line_number":270,"context_line":""},{"line_number":271,"context_line":"*  Create requested VGPU when spawn an instance which include a pass-through"}],"source_content_type":"text/x-rst","patch_set":8,"id":"bab6814e_a06b3ff0","line":268,"range":{"start_line":268,"start_character":3,"end_line":268,"end_character":8},"in_reply_to":"bab6814e_7a0f4988","updated":"2016-05-20 06:27:01.000000000","message":"Done","commit_id":"3bccadf215252f6b11e4b32bcb0ed9209f839415"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"52af1a0e9a441eb5bb643128872e89ea69eb6a30","unresolved":false,"context_lines":[{"line_number":134,"context_line":"        | 0000:00:02.0 | 8086      |    041a    | Type-PF|    None     |"},{"line_number":135,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"        The fake PCIs are as:"},{"line_number":138,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":139,"context_line":"        | address      | vendor_id | product_id |dev_type|vf_model_name|"},{"line_number":140,"context_line":"        +--------------+-----------+------------+--------+-------------+"}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_6b016806","line":137,"range":{"start_line":137,"start_character":8,"end_line":137,"end_character":29},"updated":"2016-05-25 10:29:31.000000000","message":"the fake PCIs can be more than 8?","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"8b184b275c561f44fe97869a42d88edf0091262a","unresolved":false,"context_lines":[{"line_number":134,"context_line":"        | 0000:00:02.0 | 8086      |    041a    | Type-PF|    None     |"},{"line_number":135,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"        The fake PCIs are as:"},{"line_number":138,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":139,"context_line":"        | address      | vendor_id | product_id |dev_type|vf_model_name|"},{"line_number":140,"context_line":"        +--------------+-----------+------------+--------+-------------+"}],"source_content_type":"text/x-rst","patch_set":9,"id":"9abb7d3a_63ee0aee","line":137,"range":{"start_line":137,"start_character":8,"end_line":137,"end_character":29},"in_reply_to":"9abb7d3a_78db551c","updated":"2016-05-27 07:37:34.000000000","message":"ACK.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"76ad517c03ab29c872e5a4d370efbe97afae9fbb","unresolved":false,"context_lines":[{"line_number":134,"context_line":"        | 0000:00:02.0 | 8086      |    041a    | Type-PF|    None     |"},{"line_number":135,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":136,"context_line":""},{"line_number":137,"context_line":"        The fake PCIs are as:"},{"line_number":138,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":139,"context_line":"        | address      | vendor_id | product_id |dev_type|vf_model_name|"},{"line_number":140,"context_line":"        +--------------+-----------+------------+--------+-------------+"}],"source_content_type":"text/x-rst","patch_set":9,"id":"9abb7d3a_78db551c","line":137,"range":{"start_line":137,"start_character":8,"end_line":137,"end_character":29},"in_reply_to":"bab6814e_6b016806","updated":"2016-05-27 07:14:57.000000000","message":"Yes, there is maximal restriction on the function field - MAX_FUNC \u003d 0x7. So it’s not able to support\n\u003e\u003d8VFs per PF if we address VF by only increase the function# value. But if we generate addresses\nby referring to ARI(Alternative Routing ID), it should be able to resolve this problem.\n\n- The existing Openstack DBSF notation for PCI address: Domain:Bus:Slot.function (16bit:8bit:5bit:3bit)\n- Use the following method to generate the fake PCI’s address for VFs:\n1.\tThe function(PF/VF) address space (slot + function): 0x0000 – 0xFFFF; \n2.\tdetermine VF’s offset: \nVF offset \u003d Max PF’s address + \u003csafe margin\u003e \u003d\u003e the margin is used to avoid overlap between PF and VF addresses.\n3.\tthe VF address starts from the offset one by one; Use the existing field of parent_addr to associate VF to PF.\n4.\tConvert the address back to the form of “slot.function” supported by Nova currently.\nWith this way, it should be able to support up to 256 functions (PF + VFs); and the needed change is almost restricted\nin XenAPI driver - so less impact on general code.\n\nDo you think if it’s an acceptable method? Or any more comments? Thanks very much.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":2750,"name":"Sean Dague","email":"sean@dague.net","username":"sdague"},"change_message_id":"60fafc375c23ddd790030bb5b0e6628fb0c9647b","unresolved":false,"context_lines":[{"line_number":186,"context_line":""},{"line_number":187,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"* nova flavor-key m1.medium set \"pci_passthrough:alias\"\u003d\"vgpu1:1\""},{"line_number":190,"context_line":""},{"line_number":191,"context_line":"**Use the above flavor to boot VM**"},{"line_number":192,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_c323dba5","line":189,"updated":"2016-05-20 12:47:02.000000000","message":"This is an API change right, that key does not currently exist anywhere.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"c577146cc4ea2510edbf73412d504a379c4d3fc4","unresolved":false,"context_lines":[{"line_number":186,"context_line":""},{"line_number":187,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"* nova flavor-key m1.medium set \"pci_passthrough:alias\"\u003d\"vgpu1:1\""},{"line_number":190,"context_line":""},{"line_number":191,"context_line":"**Use the above flavor to boot VM**"},{"line_number":192,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_abf07067","line":189,"in_reply_to":"bab6814e_35905d4e","updated":"2016-05-25 10:25:57.000000000","message":"Cool. Thanks all for making it more clear.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"3821f702ea5c7a545df97a9a9b1c7297538c495c","unresolved":false,"context_lines":[{"line_number":186,"context_line":""},{"line_number":187,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"* nova flavor-key m1.medium set \"pci_passthrough:alias\"\u003d\"vgpu1:1\""},{"line_number":190,"context_line":""},{"line_number":191,"context_line":"**Use the above flavor to boot VM**"},{"line_number":192,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_da8e6026","line":189,"in_reply_to":"bab6814e_5aa4a906","updated":"2016-05-25 09:32:08.000000000","message":"We should point to the code here, I am not sure about that wiki page.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"21d49260cbf6c727f4015a11761a2eb710ce62ca","unresolved":false,"context_lines":[{"line_number":186,"context_line":""},{"line_number":187,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"* nova flavor-key m1.medium set \"pci_passthrough:alias\"\u003d\"vgpu1:1\""},{"line_number":190,"context_line":""},{"line_number":191,"context_line":"**Use the above flavor to boot VM**"},{"line_number":192,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_faa1a447","line":189,"in_reply_to":"bab6814e_7aedb4b6","updated":"2016-05-25 09:40:17.000000000","message":"Cool, so we totally need some docs for how all this stuff actually works. We might have some, I am just not sure where they live right now. I know we have NUMA docs in the review queue somewhere.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"608413669f5326fd21ede5a5220c673e5f48f8b6","unresolved":false,"context_lines":[{"line_number":186,"context_line":""},{"line_number":187,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"* nova flavor-key m1.medium set \"pci_passthrough:alias\"\u003d\"vgpu1:1\""},{"line_number":190,"context_line":""},{"line_number":191,"context_line":"**Use the above flavor to boot VM**"},{"line_number":192,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_5aa4a906","line":189,"in_reply_to":"bab6814e_c323dba5","updated":"2016-05-23 11:00:17.000000000","message":"No, this is how the existing passthrough pci works. See https://wiki.openstack.org/wiki/Pci_passthrough","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":12171,"name":"Moshe Levi","email":"moshele@nvidia.com","username":"moshele"},"change_message_id":"d8acb47d2c62b729a3cfaba67566b143e596fb9f","unresolved":false,"context_lines":[{"line_number":186,"context_line":""},{"line_number":187,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"* nova flavor-key m1.medium set \"pci_passthrough:alias\"\u003d\"vgpu1:1\""},{"line_number":190,"context_line":""},{"line_number":191,"context_line":"**Use the above flavor to boot VM**"},{"line_number":192,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_7aedb4b6","line":189,"in_reply_to":"bab6814e_da8e6026","updated":"2016-05-25 09:34:39.000000000","message":"see https://github.com/openstack/nova/blob/master/nova/pci/request.py#L181-L185","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":12171,"name":"Moshe Levi","email":"moshele@nvidia.com","username":"moshele"},"change_message_id":"f4e867ccbd7ecc6db2562c274fd9e6e702de248e","unresolved":false,"context_lines":[{"line_number":186,"context_line":""},{"line_number":187,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":188,"context_line":""},{"line_number":189,"context_line":"* nova flavor-key m1.medium set \"pci_passthrough:alias\"\u003d\"vgpu1:1\""},{"line_number":190,"context_line":""},{"line_number":191,"context_line":"**Use the above flavor to boot VM**"},{"line_number":192,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_35905d4e","line":189,"in_reply_to":"bab6814e_faa1a447","updated":"2016-05-25 09:45:36.000000000","message":"so in the SR-IOV sub meeting we improved all SR-IOV/PCI/NUMA documentation \nsee this commit for pci-passthrough\nhttps://review.openstack.org/#/c/312234/\n\nyou can see in https://etherpad.openstack.org/p/sriov_meeting_agenda all our documentation update\n\nwe are only missing the pf passthrough at the moment","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"52af1a0e9a441eb5bb643128872e89ea69eb6a30","unresolved":false,"context_lines":[{"line_number":197,"context_line":"Alternatives"},{"line_number":198,"context_line":"------------"},{"line_number":199,"context_line":""},{"line_number":200,"context_line":"It can also be implemented by adding a new VGPU resource type. But per the"},{"line_number":201,"context_line":"discussion, it\u0027s not worthy to do that as the relationship between PGPU"},{"line_number":202,"context_line":"and VGPU is very similar as the relationship between PF and VF in SR-IOV"},{"line_number":203,"context_line":"PCI. The existing PCI logic can be re-used to handle similar things for"},{"line_number":204,"context_line":"VGPU. Further more, AMD\u0027s VPUG solution is basing on SR-IOV."},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"Data model impact"},{"line_number":207,"context_line":"-----------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_cb17b452","line":204,"range":{"start_line":200,"start_character":1,"end_line":204,"end_character":60},"updated":"2016-05-25 10:29:31.000000000","message":"I have checked with the GVT developer, the pre-define mode for XENGT to generate several VGPV devices is not available.\n\nwe are waiting for Citrix\u0027s hypervisor and kernel developers reply.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"b7f5658c28a9f4658ac6afd174146d2012e0357e","unresolved":false,"context_lines":[{"line_number":197,"context_line":"Alternatives"},{"line_number":198,"context_line":"------------"},{"line_number":199,"context_line":""},{"line_number":200,"context_line":"It can also be implemented by adding a new VGPU resource type. But per the"},{"line_number":201,"context_line":"discussion, it\u0027s not worthy to do that as the relationship between PGPU"},{"line_number":202,"context_line":"and VGPU is very similar as the relationship between PF and VF in SR-IOV"},{"line_number":203,"context_line":"PCI. The existing PCI logic can be re-used to handle similar things for"},{"line_number":204,"context_line":"VGPU. Further more, AMD\u0027s VPUG solution is basing on SR-IOV."},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"Data model impact"},{"line_number":207,"context_line":"-----------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"9abb7d3a_6f76f13f","line":204,"range":{"start_line":200,"start_character":1,"end_line":204,"end_character":60},"in_reply_to":"bab6814e_483d31dc","updated":"2016-05-27 03:38:05.000000000","message":"GPU flavors is a combination　problem for the hypervisor admin. \n\nThe admin need forecasts resource usage to make different GPU models. \n\nDifferent combination come out different total fake pci devices. \n\nI agree: \nVS on-demand resource allocation,  it do can make nova manage the VGPU more simple.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"fb8939656be8669523332a5ff56406d3efb1a7a1","unresolved":false,"context_lines":[{"line_number":197,"context_line":"Alternatives"},{"line_number":198,"context_line":"------------"},{"line_number":199,"context_line":""},{"line_number":200,"context_line":"It can also be implemented by adding a new VGPU resource type. But per the"},{"line_number":201,"context_line":"discussion, it\u0027s not worthy to do that as the relationship between PGPU"},{"line_number":202,"context_line":"and VGPU is very similar as the relationship between PF and VF in SR-IOV"},{"line_number":203,"context_line":"PCI. The existing PCI logic can be re-used to handle similar things for"},{"line_number":204,"context_line":"VGPU. Further more, AMD\u0027s VPUG solution is basing on SR-IOV."},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"Data model impact"},{"line_number":207,"context_line":"-----------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_c459575d","line":204,"range":{"start_line":200,"start_character":1,"end_line":204,"end_character":60},"in_reply_to":"bab6814e_a75a6028","updated":"2016-05-25 14:21:05.000000000","message":"Hi Bob Ball：\n\n I think the Alternative solution looks better. This spec is really some hack for XenGT \n \n So you mean the GVT-g devices do not exist or they are just place holder before VM start. \n \n XenGT do not need pre-define mode. Jianghua Wang\u0027s previous reply is not right for XenGT. \n \n I just wonder how do you define the aperture size for each VGPU?\n \n Minimum Aperture size requirements  is different for Windows and linux. how you get the maximum number?","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"7d77b7b51362b8bc48a1b1f08ab735e70bf2b3f1","unresolved":false,"context_lines":[{"line_number":197,"context_line":"Alternatives"},{"line_number":198,"context_line":"------------"},{"line_number":199,"context_line":""},{"line_number":200,"context_line":"It can also be implemented by adding a new VGPU resource type. But per the"},{"line_number":201,"context_line":"discussion, it\u0027s not worthy to do that as the relationship between PGPU"},{"line_number":202,"context_line":"and VGPU is very similar as the relationship between PF and VF in SR-IOV"},{"line_number":203,"context_line":"PCI. The existing PCI logic can be re-used to handle similar things for"},{"line_number":204,"context_line":"VGPU. Further more, AMD\u0027s VPUG solution is basing on SR-IOV."},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"Data model impact"},{"line_number":207,"context_line":"-----------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_483d31dc","line":204,"range":{"start_line":200,"start_character":1,"end_line":204,"end_character":60},"in_reply_to":"bab6814e_ad87965f","updated":"2016-05-26 17:07:01.000000000","message":"I honestly see the models just like GPU flavors. Its a very handy abstraction that simplifies capacity management.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"a711695ea8545570496ea11dc8c65c8d70bc0c79","unresolved":false,"context_lines":[{"line_number":197,"context_line":"Alternatives"},{"line_number":198,"context_line":"------------"},{"line_number":199,"context_line":""},{"line_number":200,"context_line":"It can also be implemented by adding a new VGPU resource type. But per the"},{"line_number":201,"context_line":"discussion, it\u0027s not worthy to do that as the relationship between PGPU"},{"line_number":202,"context_line":"and VGPU is very similar as the relationship between PF and VF in SR-IOV"},{"line_number":203,"context_line":"PCI. The existing PCI logic can be re-used to handle similar things for"},{"line_number":204,"context_line":"VGPU. Further more, AMD\u0027s VPUG solution is basing on SR-IOV."},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"Data model impact"},{"line_number":207,"context_line":"-----------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_ad87965f","line":204,"range":{"start_line":200,"start_character":1,"end_line":204,"end_character":60},"in_reply_to":"bab6814e_c459575d","updated":"2016-05-26 14:54:37.000000000","message":"The alternative is indeed more flexible, but comments at https://review.openstack.org/#/c/229351/ from nova core reviewers clearly preferred an SR-IOV-like approach.\nYes, \u0027graphics\u0027 could be split into GPU and memory, but I would personally feel that is much more fine grained than an administrator would want to expose in the near future.  I believe that exposing \u0027models\u0027 of a VGPU is a more realistic use case.\nThese models would be interpreted by the hypervisor to get the aperture size requirements (or memory / GPU slice / anything) when setting up the virtual GPU.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"71cc3bc865c50a5bbcbb5e4cc9e043f8472b0332","unresolved":false,"context_lines":[{"line_number":197,"context_line":"Alternatives"},{"line_number":198,"context_line":"------------"},{"line_number":199,"context_line":""},{"line_number":200,"context_line":"It can also be implemented by adding a new VGPU resource type. But per the"},{"line_number":201,"context_line":"discussion, it\u0027s not worthy to do that as the relationship between PGPU"},{"line_number":202,"context_line":"and VGPU is very similar as the relationship between PF and VF in SR-IOV"},{"line_number":203,"context_line":"PCI. The existing PCI logic can be re-used to handle similar things for"},{"line_number":204,"context_line":"VGPU. Further more, AMD\u0027s VPUG solution is basing on SR-IOV."},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"Data model impact"},{"line_number":207,"context_line":"-----------------"}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_a75a6028","line":204,"range":{"start_line":200,"start_character":1,"end_line":204,"end_character":60},"in_reply_to":"bab6814e_cb17b452","updated":"2016-05-25 11:02:17.000000000","message":"In the XenServer case, we already generate \"VGPU\"s based on the aperture size of the physical GPU, which gives us the maximum number.\nThe actual GVT-g devices are not initialised until runtime.\n\nA pre-define mode is not required in the XenGT code and no further changes are needed on top of XenServer 7.0 to use this capability.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":782,"name":"John Garbutt","email":"john@johngarbutt.com","username":"johngarbutt"},"change_message_id":"be34dd601128bdc9fb0e3769d6baf5fc0a83bd1a","unresolved":false,"context_lines":[{"line_number":202,"context_line":"and VGPU is very similar as the relationship between PF and VF in SR-IOV"},{"line_number":203,"context_line":"PCI. The existing PCI logic can be re-used to handle similar things for"},{"line_number":204,"context_line":"VGPU. Further more, AMD\u0027s VPUG solution is basing on SR-IOV."},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"Data model impact"},{"line_number":207,"context_line":"-----------------"},{"line_number":208,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_351b3d1e","line":205,"updated":"2016-05-25 09:43:59.000000000","message":"So here we only have one GPU type exposed per host, for simplicity.\n\nWe should cover why we are not allowing multiple types to be exposed, at least at the moment.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"c577146cc4ea2510edbf73412d504a379c4d3fc4","unresolved":false,"context_lines":[{"line_number":202,"context_line":"and VGPU is very similar as the relationship between PF and VF in SR-IOV"},{"line_number":203,"context_line":"PCI. The existing PCI logic can be re-used to handle similar things for"},{"line_number":204,"context_line":"VGPU. Further more, AMD\u0027s VPUG solution is basing on SR-IOV."},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"Data model impact"},{"line_number":207,"context_line":"-----------------"},{"line_number":208,"context_line":""}],"source_content_type":"text/x-rst","patch_set":9,"id":"bab6814e_6ba5e845","line":205,"in_reply_to":"bab6814e_351b3d1e","updated":"2016-05-25 10:25:57.000000000","message":"Good point. Sure, will include that in the new patch set.","commit_id":"4def3679021df99efcf6b00fd557d0e11db5114c"},{"author":{"_account_id":14131,"name":"shaohef","email":"shaohe.feng@intel.com","username":"shaohefeng"},"change_message_id":"05a058bddb8b39e773bd3bbe166991af32a87565","unresolved":false,"context_lines":[{"line_number":137,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":138,"context_line":"        | 0000:00:02.1 | 8086      |    041a    | Type-VF|   VGPU-1    |"},{"line_number":139,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":140,"context_line":"        | 0000:00:02.2 | 8086      |    041a    | Type-VF|   VGPU-1    |"},{"line_number":141,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":142,"context_line":""},{"line_number":143,"context_line":"        The PCI pools are as:"}],"source_content_type":"text/x-rst","patch_set":10,"id":"9abb7d3a_c38ed626","line":140,"range":{"start_line":140,"start_character":10,"end_line":140,"end_character":23},"updated":"2016-05-27 07:40:23.000000000","message":"As we discussed:\nNote the VF number can be up to more than 8","commit_id":"8db837f36750d327ac0cc12c84278484d2fac8dc"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"98796ca51317a4e5642c47066a1e55f4b32c8c14","unresolved":false,"context_lines":[{"line_number":130,"context_line":"           ARI-FUN, so firslty convert PF\u0027s Slot.function to ARI-FUN:"},{"line_number":131,"context_line":"             ARI-FUN \u003d Slot \u003c\u003c 3 + Function"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"         - The 1st VF\u0027s ARI-FUN \u003d Max PF\u0027s ARI-FUN + 1"},{"line_number":134,"context_line":""},{"line_number":135,"context_line":"         - The n-th VF\u0027s ARI-FUN \u003d (n-1)th VF\u0027s ARI-FUN + 1"},{"line_number":136,"context_line":""}],"source_content_type":"text/x-rst","patch_set":11,"id":"9abb7d3a_f5b9feed","line":133,"updated":"2016-05-27 13:17:45.000000000","message":"This is confusing, and IMO too technical for the spec.  Can we have a real example for what this would look like?\n\nI don\u0027t think we need a new term (ARI-FUN).\n\nI \u003cthink\u003e the proposal is to:\n* Find the final PCI device on this bus (which may be this device)\n* Increase the device number by 1, and start using functions increasing from there.\n\nFor example:\n0000:01.0 - Graphics device\n0000:02.0 to 0000:06.0 - Non-graphics device\n0000:07.0 to 0000:08.7 - 16 VFs, linked to 0000:01.0 somehow?\n\nYou\u0027ll need to address what happens if there are two devices we are trying to fake VFs for on the same bus (probably say we will error?), and also point out that PCIe devices (e.g. GRID, AMD MxGPU) have a whole bus for themselves, so this workaround is specific for integrated virtualised GPU such as GVT-g","commit_id":"80a0ecc00f0bc14da8b93489ce8140d960c97010"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"3cefe1bd553651736feb8115d78b958b0e1befc6","unresolved":false,"context_lines":[{"line_number":130,"context_line":"           ARI-FUN, so firslty convert PF\u0027s Slot.function to ARI-FUN:"},{"line_number":131,"context_line":"             ARI-FUN \u003d Slot \u003c\u003c 3 + Function"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"         - The 1st VF\u0027s ARI-FUN \u003d Max PF\u0027s ARI-FUN + 1"},{"line_number":134,"context_line":""},{"line_number":135,"context_line":"         - The n-th VF\u0027s ARI-FUN \u003d (n-1)th VF\u0027s ARI-FUN + 1"},{"line_number":136,"context_line":""}],"source_content_type":"text/x-rst","patch_set":11,"id":"9abb7d3a_55d8caef","line":133,"in_reply_to":"9abb7d3a_f5b9feed","updated":"2016-05-27 13:23:17.000000000","message":"Thanks for the comments. I will update it accordingly.","commit_id":"80a0ecc00f0bc14da8b93489ce8140d960c97010"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"07e08aa501da4a20fe19f1db1d61119338f91bd8","unresolved":false,"context_lines":[{"line_number":130,"context_line":"           ARI-FUN, so firslty convert PF\u0027s Slot.function to ARI-FUN:"},{"line_number":131,"context_line":"             ARI-FUN \u003d Slot \u003c\u003c 3 + Function"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"         - The 1st VF\u0027s ARI-FUN \u003d Max PF\u0027s ARI-FUN + 1"},{"line_number":134,"context_line":""},{"line_number":135,"context_line":"         - The n-th VF\u0027s ARI-FUN \u003d (n-1)th VF\u0027s ARI-FUN + 1"},{"line_number":136,"context_line":""}],"source_content_type":"text/x-rst","patch_set":11,"id":"9abb7d3a_db2f9b3c","line":133,"in_reply_to":"9abb7d3a_f5b9feed","updated":"2016-05-30 02:48:44.000000000","message":"We can attach the VFs to PFs by using the existing PCI field \"parent_addr\". It can just depend on this field to determine which VF belong to which PF. So this implement should be able to cover the scenario of \"there are two devices we are trying to fake VFs for on the same bus\". \nI think we don\u0027t have to distinguish the case of GVT-g from \"GRID, AMD\" especially; as the implement just to find out the empty slot in the bus. There is no difference if the GPU device occupied the whole bus or not. As a consistent solution, the fake VFs just start addressing from the next available slot.","commit_id":"80a0ecc00f0bc14da8b93489ce8140d960c97010"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"7fedfe933cbaf38a4068222fb40af618b64640b8","unresolved":false,"context_lines":[{"line_number":160,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":161,"context_line":"        | 0000:00:03.0 | 8086      |    041a    | Type-VF|   VGPU-1    |"},{"line_number":162,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":163,"context_line":"        | 0000:00:03.0 | 8086      |    041a    | Type-VF|   VGPU-1    |"},{"line_number":164,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":165,"context_line":""},{"line_number":166,"context_line":"        The PCI pools are as:"}],"source_content_type":"text/x-rst","patch_set":15,"id":"9abb7d3a_ade866e3","line":163,"updated":"2016-05-31 08:37:15.000000000","message":"03.1","commit_id":"af1e844bdfa4f8bde29b503b9b5612e13aa53c4e"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"bf4a925ffb25a061496549fbf9b2a4482c18a0ee","unresolved":false,"context_lines":[{"line_number":160,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":161,"context_line":"        | 0000:00:03.0 | 8086      |    041a    | Type-VF|   VGPU-1    |"},{"line_number":162,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":163,"context_line":"        | 0000:00:03.0 | 8086      |    041a    | Type-VF|   VGPU-1    |"},{"line_number":164,"context_line":"        +--------------+-----------+------------+--------+-------------+"},{"line_number":165,"context_line":""},{"line_number":166,"context_line":"        The PCI pools are as:"}],"source_content_type":"text/x-rst","patch_set":15,"id":"9abb7d3a_c5e93ee8","line":163,"in_reply_to":"9abb7d3a_ade866e3","updated":"2016-05-31 09:55:02.000000000","message":"Done","commit_id":"af1e844bdfa4f8bde29b503b9b5612e13aa53c4e"},{"author":{"_account_id":1779,"name":"Daniel Berrange","email":"berrange@redhat.com","username":"berrange"},"change_message_id":"feb90d50019aa4acfca3594e94f4b9fbf55ae78c","unresolved":false,"context_lines":[{"line_number":115,"context_line":"         Domain:Bus:Slot.Function (16bits:8bits:5bits.3bits)"},{"line_number":116,"context_line":"       The maximal function number is 7. In order to support more than 8"},{"line_number":117,"context_line":"       VFs for VGPU, we will use the empty slots to address the fake VFs."},{"line_number":118,"context_line":"       The VF\u0027s addresses will be generated as the following:"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"       * VF\u0027s Domain:Bus \u003d the associated PF\u0027s Domain:Bus"},{"line_number":121,"context_line":""}],"source_content_type":"text/x-rst","patch_set":16,"id":"9abb7d3a_c638cdd5","line":118,"range":{"start_line":118,"start_character":60,"end_line":118,"end_character":61},"updated":"2016-06-01 15:59:29.000000000","message":"I\u0027m wondering if we should not generalize the DB schema a little more, so we don\u0027t have to squash everything into a PCI address format. I think this would help other features such as virtual TPMs, and FPGA support in Nova. Basically thinking of the PCI device tracking code as actually being \u0027hardware device tracking\u0027.\n\neg we could add an \u0027address_type\u0027 field. If omitted it would default to \u0027pci\u0027 for back compat. For vGPUs which are real PCI devices, we would use address_type\u003dpci and use a normal PCI devices. For vGPUs which are *not* real PCI devices, we could invent a different address_type. eg address_type\u003dvgpu perhaps, and just use a single unique integer as the vgpu address, or we could use the pGPU\u0027s PCI addres, concatenated with an integer to indicate the vGPU number ?","commit_id":"3a033a9cb70d95a8a410ca02dead0107d27cde84"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"61eac611f8d9f3480a6bf554dfc89b7cfff7ab3a","unresolved":false,"context_lines":[{"line_number":115,"context_line":"         Domain:Bus:Slot.Function (16bits:8bits:5bits.3bits)"},{"line_number":116,"context_line":"       The maximal function number is 7. In order to support more than 8"},{"line_number":117,"context_line":"       VFs for VGPU, we will use the empty slots to address the fake VFs."},{"line_number":118,"context_line":"       The VF\u0027s addresses will be generated as the following:"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"       * VF\u0027s Domain:Bus \u003d the associated PF\u0027s Domain:Bus"},{"line_number":121,"context_line":""}],"source_content_type":"text/x-rst","patch_set":16,"id":"9abb7d3a_e95bf9f4","line":118,"in_reply_to":"9abb7d3a_b5bae86f","updated":"2016-06-02 09:29:49.000000000","message":"I see.  I suspect this addition to the PCI code would need a ML discussion?","commit_id":"3a033a9cb70d95a8a410ca02dead0107d27cde84"},{"author":{"_account_id":1779,"name":"Daniel Berrange","email":"berrange@redhat.com","username":"berrange"},"change_message_id":"6b95999ec87df9b5102126f6d65bc25ace5e7151","unresolved":false,"context_lines":[{"line_number":115,"context_line":"         Domain:Bus:Slot.Function (16bits:8bits:5bits.3bits)"},{"line_number":116,"context_line":"       The maximal function number is 7. In order to support more than 8"},{"line_number":117,"context_line":"       VFs for VGPU, we will use the empty slots to address the fake VFs."},{"line_number":118,"context_line":"       The VF\u0027s addresses will be generated as the following:"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"       * VF\u0027s Domain:Bus \u003d the associated PF\u0027s Domain:Bus"},{"line_number":121,"context_line":""}],"source_content_type":"text/x-rst","patch_set":16,"id":"9abb7d3a_b5bae86f","line":118,"range":{"start_line":118,"start_character":60,"end_line":118,"end_character":61},"in_reply_to":"9abb7d3a_b6eb32db","updated":"2016-06-02 08:34:18.000000000","message":"@Bob, the way that VFIO / vGPU integration will work is that QEMU will see the device as a regular PCI device, but IIUC from the kernel POV they will still not look like PCI devices unless the vGPU is actually using SRIOV. IOW, I believe that libvirt will need the address_type\u003dvgpu concept too. \n\nI realize that the change i suggest will require some refactoring of the PCI device code and probably renaming of the Nova object from PCIDevice to simply HostDevice to mimimize confusion. I see that as mostly unavoidable, since trying to invent fake PCI addresses is putting a square peg into a round hole and will cause as many problems as it solves IMHO.","commit_id":"3a033a9cb70d95a8a410ca02dead0107d27cde84"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"d9632deaefe4e51af298557028f8a8c8b38357a1","unresolved":false,"context_lines":[{"line_number":115,"context_line":"         Domain:Bus:Slot.Function (16bits:8bits:5bits.3bits)"},{"line_number":116,"context_line":"       The maximal function number is 7. In order to support more than 8"},{"line_number":117,"context_line":"       VFs for VGPU, we will use the empty slots to address the fake VFs."},{"line_number":118,"context_line":"       The VF\u0027s addresses will be generated as the following:"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"       * VF\u0027s Domain:Bus \u003d the associated PF\u0027s Domain:Bus"},{"line_number":121,"context_line":""}],"source_content_type":"text/x-rst","patch_set":16,"id":"9abb7d3a_ae790495","line":118,"range":{"start_line":118,"start_character":60,"end_line":118,"end_character":61},"in_reply_to":"9abb7d3a_b6eb32db","updated":"2016-06-02 03:21:12.000000000","message":"Agree. If other drivers implement vGPUs as real PCIs and only \nXenAPI use fake PCIs. It seems not worthy to add this new \naddress_type\u003dvgpu and change PCI\u0027s logic at the\n common layer. I\u0027m not sure but if xen applies VFIO too in the\n future, VGPUs in XenAPI will be real PCIs. Then it will be much\n easier for us to convert it back to normal PCI mode if we go with\n our current proposal.","commit_id":"3a033a9cb70d95a8a410ca02dead0107d27cde84"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"b0aaf94fb515979b239b623402854cdeffc43e5d","unresolved":false,"context_lines":[{"line_number":115,"context_line":"         Domain:Bus:Slot.Function (16bits:8bits:5bits.3bits)"},{"line_number":116,"context_line":"       The maximal function number is 7. In order to support more than 8"},{"line_number":117,"context_line":"       VFs for VGPU, we will use the empty slots to address the fake VFs."},{"line_number":118,"context_line":"       The VF\u0027s addresses will be generated as the following:"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"       * VF\u0027s Domain:Bus \u003d the associated PF\u0027s Domain:Bus"},{"line_number":121,"context_line":""}],"source_content_type":"text/x-rst","patch_set":16,"id":"9abb7d3a_f7df79d3","line":118,"range":{"start_line":118,"start_character":60,"end_line":118,"end_character":61},"in_reply_to":"9abb7d3a_c638cdd5","updated":"2016-06-01 17:09:43.000000000","message":"Thanks Daniel. Understand it will look much elegant by generalize the PCI device and use different type to distinguish VGPU. But in that way, we have to change the existing logic on PCI resource tracking, schedule... the needed change is large. And it also has much dependence on some on-going specs e.g. pci-stat, resource objects, resource provider. I don\u0027t think that can be achieved shortly. \n  Actually, 6 months ago we also considered to use a new resource type to tracking VGPU: see https://review.openstack.org/#/c/229351/; but it was rejected due to dependence on some todo specs and suggested to use fake PCI.\n  The biggest benefit with this proposal is that the majority work is done in the layer of XenAPI driver. From upstream, VGPUs can be treated as normal PCI devices. so less impact on upstream code and less dependence on the ongoing specs.\n  So could we use this proposal to enable vGPU as the first step and consider the evolution in the future release?\n  thanks again.","commit_id":"3a033a9cb70d95a8a410ca02dead0107d27cde84"},{"author":{"_account_id":1779,"name":"Daniel Berrange","email":"berrange@redhat.com","username":"berrange"},"change_message_id":"612e7662b9abb956eeb5451606633330e7497359","unresolved":false,"context_lines":[{"line_number":115,"context_line":"         Domain:Bus:Slot.Function (16bits:8bits:5bits.3bits)"},{"line_number":116,"context_line":"       The maximal function number is 7. In order to support more than 8"},{"line_number":117,"context_line":"       VFs for VGPU, we will use the empty slots to address the fake VFs."},{"line_number":118,"context_line":"       The VF\u0027s addresses will be generated as the following:"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"       * VF\u0027s Domain:Bus \u003d the associated PF\u0027s Domain:Bus"},{"line_number":121,"context_line":""}],"source_content_type":"text/x-rst","patch_set":16,"id":"9abb7d3a_fb0f3a86","line":118,"in_reply_to":"9abb7d3a_e95bf9f4","updated":"2016-06-02 10:21:55.000000000","message":"Yeah, possibly even need to have the PCI refactoring listed as an explicit spec, which this depends on for sake of clarity. Could particularly benefit from Jay Pipes\u0027 input here","commit_id":"3a033a9cb70d95a8a410ca02dead0107d27cde84"},{"author":{"_account_id":6735,"name":"Bob Ball","email":"bob.ball@citrix.com","username":"bob-ball"},"change_message_id":"2cda29c114bb4840f16e0d167db9b09b71d7f946","unresolved":false,"context_lines":[{"line_number":115,"context_line":"         Domain:Bus:Slot.Function (16bits:8bits:5bits.3bits)"},{"line_number":116,"context_line":"       The maximal function number is 7. In order to support more than 8"},{"line_number":117,"context_line":"       VFs for VGPU, we will use the empty slots to address the fake VFs."},{"line_number":118,"context_line":"       The VF\u0027s addresses will be generated as the following:"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"       * VF\u0027s Domain:Bus \u003d the associated PF\u0027s Domain:Bus"},{"line_number":121,"context_line":""}],"source_content_type":"text/x-rst","patch_set":16,"id":"9abb7d3a_b6eb32db","line":118,"range":{"start_line":118,"start_character":60,"end_line":118,"end_character":61},"in_reply_to":"9abb7d3a_f7df79d3","updated":"2016-06-01 17:29:02.000000000","message":"I\u0027d be concerned that adding an address_type to the \"PCI\" device tracking code would be confusing; everyone would assume these were just PCI devices.  It is also likely to cause driver differences down the line, if, as you say, virtualised GPU devices will be faked as actual PCI addresses in the linux kernel for use by libvirt.\n\nIf we had an address_type\u003dvgpu then I assume it would be specific to the XenAPI driver as the libvirt code would just use the standard PCI address type?\n\nOne of the main intentions of this spec was to try and get forward compatability between the drivers so that when libvirt does get VGPU support it could use the same mechanism to provide it to VMs.","commit_id":"3a033a9cb70d95a8a410ca02dead0107d27cde84"},{"author":{"_account_id":1779,"name":"Daniel Berrange","email":"berrange@redhat.com","username":"berrange"},"change_message_id":"feb90d50019aa4acfca3594e94f4b9fbf55ae78c","unresolved":false,"context_lines":[{"line_number":321,"context_line":"[1] PCI passthrough: https://wiki.openstack.org/wiki/Pci_passthrough"},{"line_number":322,"context_line":""},{"line_number":323,"context_line":"[2] Nova PCI SR-IOV: https://github.com/openstack/nova-specs/blob/master/specs/juno/implemented/pci-passthrough-sriov.rst"},{"line_number":324,"context_line":""},{"line_number":325,"context_line":"History"},{"line_number":326,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":327,"context_line":""}],"source_content_type":"text/x-rst","patch_set":16,"id":"9abb7d3a_8b37ee4b","line":324,"updated":"2016-06-01 15:59:29.000000000","message":"This thread is probably useful material. It is the current proposal to integrate vGPU support in the linux kernel via VFIO, which ends up making vGPUs look just like PCI devices to QEMU, even if they\u0027re not really PCI devices. It sounds like there\u0027s potential for Xen to adopt VFIO too eventually.\n\nhttps://lists.gnu.org/archive/html/qemu-devel/2016-05/msg04201.html","commit_id":"3a033a9cb70d95a8a410ca02dead0107d27cde84"},{"author":{"_account_id":17920,"name":"Jianghua Wang","email":"jianghua.wang@citrix.com","username":"wjhfresh"},"change_message_id":"b0aaf94fb515979b239b623402854cdeffc43e5d","unresolved":false,"context_lines":[{"line_number":321,"context_line":"[1] PCI passthrough: https://wiki.openstack.org/wiki/Pci_passthrough"},{"line_number":322,"context_line":""},{"line_number":323,"context_line":"[2] Nova PCI SR-IOV: https://github.com/openstack/nova-specs/blob/master/specs/juno/implemented/pci-passthrough-sriov.rst"},{"line_number":324,"context_line":""},{"line_number":325,"context_line":"History"},{"line_number":326,"context_line":"\u003d\u003d\u003d\u003d\u003d\u003d\u003d"},{"line_number":327,"context_line":""}],"source_content_type":"text/x-rst","patch_set":16,"id":"9abb7d3a_d34a4854","line":324,"in_reply_to":"9abb7d3a_8b37ee4b","updated":"2016-06-01 17:09:43.000000000","message":"Thanks for this sharing. That\u0027s interesting. I will forward this info to XenServer developers. But XenServer\u0027s released vGPU feature is different.","commit_id":"3a033a9cb70d95a8a410ca02dead0107d27cde84"}],"specs/ocata/approved/xenapi-add-support-for-vgpu.rst":[{"author":{"_account_id":17973,"name":"Ludovic Beliveau","email":"lbeliveau@gmail.com","username":"lbeliveau"},"change_message_id":"06429a384389772f39d5d1ad7fdf6307f331b72d","unresolved":false,"context_lines":[{"line_number":220,"context_line":"  host_device_passthrough_whitelist\u003d\u0027["},{"line_number":221,"context_line":"  { \"vendor_id\":\"8086\",\"product_id\":\"041a\", \"group_id\":\"VGPU-1\"}]\u0027"},{"line_number":222,"context_line":"  host_device_alias\u003d\u0027{"},{"line_number":223,"context_line":"  \"name\":\"a1\", \"vendor_id\":\"8086\", \"product_id\":\"041a\", \"group_id\":\"VGPU-1\"}\u0027"},{"line_number":224,"context_line":""},{"line_number":225,"context_line":"**Configure flavor to specify the VGPU type and the count**"},{"line_number":226,"context_line":""}],"source_content_type":"text/x-rst","patch_set":18,"id":"ba5da102_ce948a8c","line":223,"updated":"2016-11-03 12:38:03.000000000","message":"You\u0027ll need to modify the pci_alias schema: https://github.com/openstack/nova/blob/master/nova/pci/request.py#L70","commit_id":"a184b852f889f0f4172cd82bc370e6128aae9e49"}]}