)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":7,"name":"Jay Pipes","email":"jaypipes@gmail.com","username":"jaypipes"},"change_message_id":"f7edae1db01f9a0353c23443edcbe78118e2b35f","unresolved":false,"context_lines":[{"line_number":7,"context_line":"Not use thread alloc policy for emulator thread"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"When CPUEmulatorThreadsPolicy and CPUThreadAllocationPolicy were both"},{"line_number":10,"context_line":"set to isolate, pcpus for emulator threads were also allocated along"},{"line_number":11,"context_line":"with thread isolation policy. (i.e. only chosen from a siblings_set"},{"line_number":12,"context_line":"where full threads are available.)"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":"For optimization purpose, this patch allows in that case to choose"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"3fa0c359_a8d1095a","line":11,"range":{"start_line":10,"start_character":62,"end_line":11,"end_character":4},"updated":"2018-02-05 15:59:14.000000000","message":"s/along with/according to the/","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"},{"author":{"_account_id":25625,"name":"Tetsuro Nakamura","email":"tetsuro.nakamura.bc@hco.ntt.co.jp","username":"tetsuro0907"},"change_message_id":"aea19be8b2f19b73ce5e4ad88633273df4711ae9","unresolved":false,"context_lines":[{"line_number":7,"context_line":"Not use thread alloc policy for emulator thread"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"When CPUEmulatorThreadsPolicy and CPUThreadAllocationPolicy were both"},{"line_number":10,"context_line":"set to isolate, pcpus for emulator threads were also allocated along"},{"line_number":11,"context_line":"with thread isolation policy. (i.e. only chosen from a siblings_set"},{"line_number":12,"context_line":"where full threads are available.)"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":"For optimization purpose, this patch allows in that case to choose"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"3fa0c359_6884330d","line":11,"range":{"start_line":10,"start_character":62,"end_line":11,"end_character":4},"in_reply_to":"3fa0c359_a8d1095a","updated":"2018-02-07 04:39:21.000000000","message":"Done","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"},{"author":{"_account_id":7,"name":"Jay Pipes","email":"jaypipes@gmail.com","username":"jaypipes"},"change_message_id":"f7edae1db01f9a0353c23443edcbe78118e2b35f","unresolved":false,"context_lines":[{"line_number":11,"context_line":"with thread isolation policy. (i.e. only chosen from a siblings_set"},{"line_number":12,"context_line":"where full threads are available.)"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":"For optimization purpose, this patch allows in that case to choose"},{"line_number":15,"context_line":"pcpus from non-fully siblings_set for emulator threads by considering"},{"line_number":16,"context_line":"pinning cpus and reserved cpus separately, adding a new function of"},{"line_number":17,"context_line":"_get_reserved()."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"3fa0c359_08bcbd03","line":14,"range":{"start_line":14,"start_character":17,"end_line":14,"end_character":24},"updated":"2018-02-05 15:59:14.000000000","message":"purposes","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"},{"author":{"_account_id":25625,"name":"Tetsuro Nakamura","email":"tetsuro.nakamura.bc@hco.ntt.co.jp","username":"tetsuro0907"},"change_message_id":"aea19be8b2f19b73ce5e4ad88633273df4711ae9","unresolved":false,"context_lines":[{"line_number":11,"context_line":"with thread isolation policy. (i.e. only chosen from a siblings_set"},{"line_number":12,"context_line":"where full threads are available.)"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":"For optimization purpose, this patch allows in that case to choose"},{"line_number":15,"context_line":"pcpus from non-fully siblings_set for emulator threads by considering"},{"line_number":16,"context_line":"pinning cpus and reserved cpus separately, adding a new function of"},{"line_number":17,"context_line":"_get_reserved()."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"3fa0c359_88873f10","line":14,"range":{"start_line":14,"start_character":17,"end_line":14,"end_character":24},"in_reply_to":"3fa0c359_08bcbd03","updated":"2018-02-07 04:39:21.000000000","message":"Done","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"},{"author":{"_account_id":7,"name":"Jay Pipes","email":"jaypipes@gmail.com","username":"jaypipes"},"change_message_id":"f7edae1db01f9a0353c23443edcbe78118e2b35f","unresolved":false,"context_lines":[{"line_number":11,"context_line":"with thread isolation policy. (i.e. only chosen from a siblings_set"},{"line_number":12,"context_line":"where full threads are available.)"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":"For optimization purpose, this patch allows in that case to choose"},{"line_number":15,"context_line":"pcpus from non-fully siblings_set for emulator threads by considering"},{"line_number":16,"context_line":"pinning cpus and reserved cpus separately, adding a new function of"},{"line_number":17,"context_line":"_get_reserved()."},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"Change-Id: I23a5142398900873364bb07d8e91595d02a7a13d"},{"line_number":20,"context_line":"Closes-Bug: #1746393"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"3fa0c359_68278166","line":17,"range":{"start_line":14,"start_character":57,"end_line":17,"end_character":16},"updated":"2018-02-05 15:59:14.000000000","message":"this is a bit confusing. how about this instead?\n\nFor optimization purposes, this patch allows emulator threads and the VM\u0027s I/O threads to be collocated on the same sibling sets of pCPUs even when both I/O thread and emulator thread are set to \"isolate\".","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"},{"author":{"_account_id":25625,"name":"Tetsuro Nakamura","email":"tetsuro.nakamura.bc@hco.ntt.co.jp","username":"tetsuro0907"},"change_message_id":"aea19be8b2f19b73ce5e4ad88633273df4711ae9","unresolved":false,"context_lines":[{"line_number":11,"context_line":"with thread isolation policy. (i.e. only chosen from a siblings_set"},{"line_number":12,"context_line":"where full threads are available.)"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":"For optimization purpose, this patch allows in that case to choose"},{"line_number":15,"context_line":"pcpus from non-fully siblings_set for emulator threads by considering"},{"line_number":16,"context_line":"pinning cpus and reserved cpus separately, adding a new function of"},{"line_number":17,"context_line":"_get_reserved()."},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"Change-Id: I23a5142398900873364bb07d8e91595d02a7a13d"},{"line_number":20,"context_line":"Closes-Bug: #1746393"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"3fa0c359_08c1ef2e","line":17,"range":{"start_line":14,"start_character":57,"end_line":17,"end_character":16},"in_reply_to":"3fa0c359_68278166","updated":"2018-02-07 04:39:21.000000000","message":"Thank you for the great suggestion. Sounds much better than the original. I changed this part according to your words.","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"},{"author":{"_account_id":27336,"name":"XiaojueGuan","email":"xiaojueguan@gmail.com","username":"XiaojueGuan"},"change_message_id":"43784c0eca25eadc9b93bdc93abadaf7c3089329","unresolved":false,"context_lines":[{"line_number":11,"context_line":"with thread isolation policy. (i.e. only chosen from a siblings_set"},{"line_number":12,"context_line":"where full threads are available.)"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":"For optimization purpose, this patch allows in that case to choose"},{"line_number":15,"context_line":"pcpus from non-fully siblings_set for emulator threads by considering"},{"line_number":16,"context_line":"pinning cpus and reserved cpus separately, adding a new function of"},{"line_number":17,"context_line":"_get_reserved()."},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"Change-Id: I23a5142398900873364bb07d8e91595d02a7a13d"},{"line_number":20,"context_line":"Closes-Bug: #1746393"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"3fa0c359_54f54982","line":17,"range":{"start_line":14,"start_character":57,"end_line":17,"end_character":16},"in_reply_to":"3fa0c359_68278166","updated":"2018-02-07 09:26:19.000000000","message":"this sounds much better, the previous one sounds much ambigous. while this looks much clear","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"}],"nova/virt/hardware.py":[{"author":{"_account_id":25625,"name":"Tetsuro Nakamura","email":"tetsuro.nakamura.bc@hco.ntt.co.jp","username":"tetsuro0907"},"change_message_id":"8904f8f56ec9a5d65eec4d3ac2770470884aeefd","unresolved":false,"context_lines":[{"line_number":804,"context_line":"        if num_cpu_reserved:"},{"line_number":805,"context_line":"            # Updates the pCPUs used based on vCPUs pinned to"},{"line_number":806,"context_line":"            # For vcpus_pinning\u003d[(0, 0), (1, 2)],"},{"line_number":807,"context_line":"            #     usable_cores\u003d[[0, 1], [1, 3], [4, 5]]"},{"line_number":808,"context_line":"            # if CPUThreadAllocationPolicy is isolated:"},{"line_number":809,"context_line":"            #     usable_cores\u003d[[4, 5]]"},{"line_number":810,"context_line":"            # else:"}],"source_content_type":"text/x-python","patch_set":2,"id":"5f93b717_0f80ccbf","line":807,"range":{"start_line":807,"start_character":18,"end_line":807,"end_character":55},"updated":"2018-01-30 11:16:13.000000000","message":"Ah, this is wrong...\nThis should be usable_cores\u003d[[0, 1], [2, 3], [4, 5]]","commit_id":"4c3aaf76b46795331e94f4269b17fdb8100e7f5f"},{"author":{"_account_id":25625,"name":"Tetsuro Nakamura","email":"tetsuro.nakamura.bc@hco.ntt.co.jp","username":"tetsuro0907"},"change_message_id":"b9a9cf287b60ae3840cf1be4646cd41e7c6a336f","unresolved":false,"context_lines":[{"line_number":804,"context_line":"        if num_cpu_reserved:"},{"line_number":805,"context_line":"            # Updates the pCPUs used based on vCPUs pinned to"},{"line_number":806,"context_line":"            # For vcpus_pinning\u003d[(0, 0), (1, 2)],"},{"line_number":807,"context_line":"            #     usable_cores\u003d[[0, 1], [1, 3], [4, 5]]"},{"line_number":808,"context_line":"            # if CPUThreadAllocationPolicy is isolated:"},{"line_number":809,"context_line":"            #     usable_cores\u003d[[4, 5]]"},{"line_number":810,"context_line":"            # else:"}],"source_content_type":"text/x-python","patch_set":2,"id":"5f93b717_007884c1","line":807,"range":{"start_line":807,"start_character":18,"end_line":807,"end_character":55},"in_reply_to":"5f93b717_0f80ccbf","updated":"2018-01-31 06:32:07.000000000","message":"Done","commit_id":"4c3aaf76b46795331e94f4269b17fdb8100e7f5f"},{"author":{"_account_id":25625,"name":"Tetsuro Nakamura","email":"tetsuro.nakamura.bc@hco.ntt.co.jp","username":"tetsuro0907"},"change_message_id":"8904f8f56ec9a5d65eec4d3ac2770470884aeefd","unresolved":false,"context_lines":[{"line_number":805,"context_line":"            # Updates the pCPUs used based on vCPUs pinned to"},{"line_number":806,"context_line":"            # For vcpus_pinning\u003d[(0, 0), (1, 2)],"},{"line_number":807,"context_line":"            #     usable_cores\u003d[[0, 1], [1, 3], [4, 5]]"},{"line_number":808,"context_line":"            # if CPUThreadAllocationPolicy is isolated:"},{"line_number":809,"context_line":"            #     usable_cores\u003d[[4, 5]]"},{"line_number":810,"context_line":"            # else:"},{"line_number":811,"context_line":"            #     usable_cores\u003d[[0],[1],[4, 5]]"},{"line_number":812,"context_line":"            for vcpu, pcpu in vcpus_pinning:"}],"source_content_type":"text/x-python","patch_set":2,"id":"5f93b717_0f9c4c0d","line":809,"range":{"start_line":808,"start_character":0,"end_line":809,"end_character":39},"updated":"2018-01-30 11:16:13.000000000","message":"if the policy is isolated and vcpus are using pcpus 0 and 2, we don\u0027t want to use their siblings of 1 and 3 for emulator threads.","commit_id":"4c3aaf76b46795331e94f4269b17fdb8100e7f5f"},{"author":{"_account_id":25625,"name":"Tetsuro Nakamura","email":"tetsuro.nakamura.bc@hco.ntt.co.jp","username":"tetsuro0907"},"change_message_id":"8904f8f56ec9a5d65eec4d3ac2770470884aeefd","unresolved":false,"context_lines":[{"line_number":807,"context_line":"            #     usable_cores\u003d[[0, 1], [1, 3], [4, 5]]"},{"line_number":808,"context_line":"            # if CPUThreadAllocationPolicy is isolated:"},{"line_number":809,"context_line":"            #     usable_cores\u003d[[4, 5]]"},{"line_number":810,"context_line":"            # else:"},{"line_number":811,"context_line":"            #     usable_cores\u003d[[0],[1],[4, 5]]"},{"line_number":812,"context_line":"            for vcpu, pcpu in vcpus_pinning:"},{"line_number":813,"context_line":"                for sib in usable_cores:"},{"line_number":814,"context_line":"                    if pcpu in sib:"}],"source_content_type":"text/x-python","patch_set":2,"id":"5f93b717_4fa6d455","line":811,"range":{"start_line":810,"start_character":0,"end_line":811,"end_character":47},"updated":"2018-01-30 11:16:13.000000000","message":"if the policy is not isolated, vcpus are using pcpus 0 and 2, but we can use their siblings for emulator threads.","commit_id":"4c3aaf76b46795331e94f4269b17fdb8100e7f5f"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"2bf49e96338d13d4d947bf262fc632dbac2ee279","unresolved":false,"context_lines":[{"line_number":812,"context_line":"            for vcpu, pcpu in vcpus_pinning:"},{"line_number":813,"context_line":"                for sib in usable_cores:"},{"line_number":814,"context_line":"                    if pcpu in sib:"},{"line_number":815,"context_line":"                        if cpu_thread_isolate:"},{"line_number":816,"context_line":"                            usable_cores.remove(sib)"},{"line_number":817,"context_line":"                        else:"},{"line_number":818,"context_line":"                            sib.remove(pcpu)"},{"line_number":819,"context_line":""},{"line_number":820,"context_line":"            # Determines the pCPUs reserved for hypervisor"}],"source_content_type":"text/x-python","patch_set":2,"id":"5f93b717_6f4cf041","line":817,"range":{"start_line":815,"start_character":0,"end_line":817,"end_character":29},"updated":"2018-01-30 10:38:01.000000000","message":"Remind me, why do we care about the \u0027isolate\u0027 policy here?","commit_id":"4c3aaf76b46795331e94f4269b17fdb8100e7f5f"},{"author":{"_account_id":25625,"name":"Tetsuro Nakamura","email":"tetsuro.nakamura.bc@hco.ntt.co.jp","username":"tetsuro0907"},"change_message_id":"8904f8f56ec9a5d65eec4d3ac2770470884aeefd","unresolved":false,"context_lines":[{"line_number":812,"context_line":"            for vcpu, pcpu in vcpus_pinning:"},{"line_number":813,"context_line":"                for sib in usable_cores:"},{"line_number":814,"context_line":"                    if pcpu in sib:"},{"line_number":815,"context_line":"                        if cpu_thread_isolate:"},{"line_number":816,"context_line":"                            usable_cores.remove(sib)"},{"line_number":817,"context_line":"                        else:"},{"line_number":818,"context_line":"                            sib.remove(pcpu)"},{"line_number":819,"context_line":""},{"line_number":820,"context_line":"            # Determines the pCPUs reserved for hypervisor"}],"source_content_type":"text/x-python","patch_set":2,"id":"5f93b717_6f8ab0bf","line":817,"range":{"start_line":815,"start_character":0,"end_line":817,"end_character":29},"in_reply_to":"5f93b717_6f4cf041","updated":"2018-01-30 11:16:13.000000000","message":"explained this along with the comment above. More intrinsically, we used to deal with reserved cpu + pinning cpu at the same time, and regardless of  isolate/prefer/require policy case, there was a mechanism to force to choose reserved cpu from a different sibling set from sibling sets where vcpus are chosen. But now they are separated so here we can choose to avoid the same sibling(isolate case) or to not care(prefer/require case).","commit_id":"4c3aaf76b46795331e94f4269b17fdb8100e7f5f"},{"author":{"_account_id":7,"name":"Jay Pipes","email":"jaypipes@gmail.com","username":"jaypipes"},"change_message_id":"f7edae1db01f9a0353c23443edcbe78118e2b35f","unresolved":false,"context_lines":[{"line_number":739,"context_line":"        \"\"\"Determines pCPUs/vCPUs mapping"},{"line_number":740,"context_line":""},{"line_number":741,"context_line":"        Determines the pCPUs/vCPUs mapping regarding the number of"},{"line_number":742,"context_line":"        threads which can be used per cores and pCPUs reserved."},{"line_number":743,"context_line":""},{"line_number":744,"context_line":"        :param threads_no: Number of host threads per cores which can"},{"line_number":745,"context_line":"                           be used to pin vCPUs according to the"}],"source_content_type":"text/x-python","patch_set":3,"id":"3fa0c359_089b5d72","line":742,"range":{"start_line":742,"start_character":43,"end_line":742,"end_character":63},"updated":"2018-02-05 15:59:14.000000000","message":"this part of the docstring is no longer valid. Please remove.","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"},{"author":{"_account_id":25625,"name":"Tetsuro Nakamura","email":"tetsuro.nakamura.bc@hco.ntt.co.jp","username":"tetsuro0907"},"change_message_id":"aea19be8b2f19b73ce5e4ad88633273df4711ae9","unresolved":false,"context_lines":[{"line_number":739,"context_line":"        \"\"\"Determines pCPUs/vCPUs mapping"},{"line_number":740,"context_line":""},{"line_number":741,"context_line":"        Determines the pCPUs/vCPUs mapping regarding the number of"},{"line_number":742,"context_line":"        threads which can be used per cores and pCPUs reserved."},{"line_number":743,"context_line":""},{"line_number":744,"context_line":"        :param threads_no: Number of host threads per cores which can"},{"line_number":745,"context_line":"                           be used to pin vCPUs according to the"}],"source_content_type":"text/x-python","patch_set":3,"id":"3fa0c359_e8da8315","line":742,"range":{"start_line":742,"start_character":43,"end_line":742,"end_character":63},"in_reply_to":"3fa0c359_089b5d72","updated":"2018-02-07 04:39:21.000000000","message":"Done","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"},{"author":{"_account_id":7,"name":"Jay Pipes","email":"jaypipes@gmail.com","username":"jaypipes"},"change_message_id":"f7edae1db01f9a0353c23443edcbe78118e2b35f","unresolved":false,"context_lines":[{"line_number":790,"context_line":"                            on a specific host NUMA node."},{"line_number":791,"context_line":"        :param vcpus_pinning: List of tuple of (pCPU, vCPU) mapping."},{"line_number":792,"context_line":"        :param num_cpu_reserved: Number of additional host CPUs which"},{"line_number":793,"context_line":"                                 needs to be reserved."},{"line_number":794,"context_line":"        :param cpu_thread_isolate: True if CPUThreadAllocationPolicy"},{"line_number":795,"context_line":"                                   is ISOLATE."},{"line_number":796,"context_line":"        \"\"\""}],"source_content_type":"text/x-python","patch_set":3,"id":"3fa0c359_489f2550","line":793,"range":{"start_line":793,"start_character":37,"end_line":793,"end_character":38},"updated":"2018-02-05 15:59:14.000000000","message":"need to be reserved.","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"},{"author":{"_account_id":25625,"name":"Tetsuro Nakamura","email":"tetsuro.nakamura.bc@hco.ntt.co.jp","username":"tetsuro0907"},"change_message_id":"aea19be8b2f19b73ce5e4ad88633273df4711ae9","unresolved":false,"context_lines":[{"line_number":790,"context_line":"                            on a specific host NUMA node."},{"line_number":791,"context_line":"        :param vcpus_pinning: List of tuple of (pCPU, vCPU) mapping."},{"line_number":792,"context_line":"        :param num_cpu_reserved: Number of additional host CPUs which"},{"line_number":793,"context_line":"                                 needs to be reserved."},{"line_number":794,"context_line":"        :param cpu_thread_isolate: True if CPUThreadAllocationPolicy"},{"line_number":795,"context_line":"                                   is ISOLATE."},{"line_number":796,"context_line":"        \"\"\""}],"source_content_type":"text/x-python","patch_set":3,"id":"3fa0c359_08d6cff2","line":793,"range":{"start_line":793,"start_character":37,"end_line":793,"end_character":38},"in_reply_to":"3fa0c359_489f2550","updated":"2018-02-07 04:39:21.000000000","message":"Done","commit_id":"ca5d339b5823cd78856a3976f151e5948ab26d16"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"630053639ddde6b3a00d44a6881e3c17b95e815e","unresolved":false,"context_lines":[{"line_number":801,"context_line":"        usable_cores \u003d list(map(lambda s: list(s), sibling_set))"},{"line_number":802,"context_line":""},{"line_number":803,"context_line":"        if num_cpu_reserved:"},{"line_number":804,"context_line":"            # Updates the pCPUs used based on vCPUs pinned to."},{"line_number":805,"context_line":"            # For the case vcpus_pinning\u003d[(0, 0), (1, 2)] and"},{"line_number":806,"context_line":"            # usable_cores\u003d[[0, 1], [2, 3], [4, 5]],"},{"line_number":807,"context_line":"            # if CPUThreadAllocationPolicy is isolated, we want"},{"line_number":808,"context_line":"            # to update usable_cores\u003d[[4, 5]]."},{"line_number":809,"context_line":"            # If CPUThreadAllocationPolicy is *not* isolated,"},{"line_number":810,"context_line":"            # we want to update usable_cores\u003d[[1],[3],[4, 5]]."},{"line_number":811,"context_line":"            for vcpu, pcpu in vcpus_pinning:"},{"line_number":812,"context_line":"                for sib in usable_cores:"},{"line_number":813,"context_line":"                    if pcpu in sib:"}],"source_content_type":"text/x-python","patch_set":4,"id":"3fa0c359_2009502b","line":810,"range":{"start_line":804,"start_character":0,"end_line":810,"end_character":62},"updated":"2018-02-07 15:48:28.000000000","message":"I get you now. Thanks for the context!","commit_id":"113724859a8f1dc3f004636e8c016d060409a1f6"}]}