)]}'
{"nova/objects/numa.py":[{"author":{"_account_id":11347,"name":"Rui Zang","email":"rui.zang@yandex.com","username":"rzang"},"change_message_id":"44ea2ff2ff68862f92d922ae633d859cbf0a89ff","unresolved":false,"context_lines":[{"line_number":115,"context_line":"        for sib in self.siblings:"},{"line_number":116,"context_line":"            if cpus \u0026 sib:"},{"line_number":117,"context_line":"                # NOTE(artom) If the intersection between cpus and sib is not"},{"line_number":118,"context_line":"                # empty - IOW, the CPU we want to pin has sibligns - pin the"},{"line_number":119,"context_line":"                # sibling as well. This is because we normally got here because"},{"line_number":120,"context_line":"                # the `isolate` CPU thread policy is set, so we don\u0027t want to"},{"line_number":121,"context_line":"                # place guest CPUs on host thread siblings."}],"source_content_type":"text/x-python","patch_set":1,"id":"bf51134e_1e48bf59","line":118,"range":{"start_line":118,"start_character":58,"end_line":118,"end_character":66},"updated":"2020-07-16 03:38:28.000000000","message":"siblings","commit_id":"de10c126e94ac11ff2023fcbd27da2e03aca2123"}]}