)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"bede9ece5bdcfe9dc3cd90de8adf8c271eba6403","unresolved":true,"context_lines":[{"line_number":10,"context_line":"has a hardware limitation of that said vaue but some NFV operators"},{"line_number":11,"context_line":"as well as other users might need more than 28 when the hardware"},{"line_number":12,"context_line":"(such as x86_64 and AMD) allows more than that limit.   Here, we set"},{"line_number":13,"context_line":"the maximum value to 64 for all of the architectures and still use"},{"line_number":14,"context_line":"a hard maximum limit of 28 for AARCH64."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"Change-Id: I71682d1d8d2f1574e7f9fe04cac1e03d7c77f0f2"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"77813a67_66bbad5f","line":13,"range":{"start_line":13,"start_character":21,"end_line":13,"end_character":23},"updated":"2023-01-20 17:37:51.000000000","message":"the limit is a limit of 32 root ports in qemu \nhttps://github.com/qemu/qemu/blob/master/docs/pcie.txt#L81 and i belive this is actully a limit that comes from the pcie spec adressing.\n\nwe do not support the extended pci adressing modes so we are limited\nby the 32bit adressing as qemu only supprot one pci domain\nhttps://github.com/qemu/qemu/blob/master/docs/pcie.txt#L196\n\n\nif we want to support more then 32 devices we woudl need to use a more compelx topology either using the root ports in multifunction mode or possibly by addign pcie extention bridges and adding the devices to the bridges.","commit_id":"ef7ffe066a10f57603478e886c5fec354cb471a3"},{"author":{"_account_id":7130,"name":"David Hill","email":"davidchill@hotmail.com","username":"dhill"},"change_message_id":"5096844f12afb8342866a2e5b9871c5f42df17b0","unresolved":true,"context_lines":[{"line_number":10,"context_line":"has a hardware limitation of that said vaue but some NFV operators"},{"line_number":11,"context_line":"as well as other users might need more than 28 when the hardware"},{"line_number":12,"context_line":"(such as x86_64 and AMD) allows more than that limit.   Here, we set"},{"line_number":13,"context_line":"the maximum value to 64 for all of the architectures and still use"},{"line_number":14,"context_line":"a hard maximum limit of 28 for AARCH64."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"Change-Id: I71682d1d8d2f1574e7f9fe04cac1e03d7c77f0f2"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"c419dc1c_d2c58f3e","line":13,"range":{"start_line":13,"start_character":21,"end_line":13,"end_character":23},"in_reply_to":"77813a67_66bbad5f","updated":"2023-02-18 00:26:31.000000000","message":"You answered my previous question .  Thanks.","commit_id":"ef7ffe066a10f57603478e886c5fec354cb471a3"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"bec278f02bafeccb635be88cccff093603e1d80d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"0540cd48_a2cb1399","updated":"2023-02-20 11:02:56.000000000","message":"im not conviceds we should just randombly be changing this without following the upstream feature process so this either need a specless blueprint of a spec.\n\nwe are past the 2023.1 FF so master is now closed for feature work until after RC1 so this cant proceed for at least 2 weeks.","commit_id":"3415868bef57bfe3be07334b154add115fa8c343"}],"nova/conf/libvirt.py":[{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"ad91bfde00983678cc352a77fc85f46cceca2131","unresolved":true,"context_lines":[{"line_number":793,"context_line":"    cfg.IntOpt(\u0027num_pcie_ports\u0027,"},{"line_number":794,"context_line":"               default\u003d0,"},{"line_number":795,"context_line":"               min\u003d0,"},{"line_number":796,"context_line":"               max\u003d64,"},{"line_number":797,"context_line":"               help\u003d \"\"\""},{"line_number":798,"context_line":"The number of PCIe ports an instance will get."},{"line_number":799,"context_line":""}],"source_content_type":"text/x-python","patch_set":2,"id":"4f47ed0d_4b0c662d","line":796,"range":{"start_line":796,"start_character":19,"end_line":796,"end_character":21},"updated":"2023-01-20 17:29:23.000000000","message":"the qemu docs sate that you can have at must 32 devices\nhttps://github.com/qemu/qemu/blob/master/docs/pcie.txt#L81","commit_id":"ef7ffe066a10f57603478e886c5fec354cb471a3"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"596516d111e3cbe8c8c18df4a5768af0f144c674","unresolved":true,"context_lines":[{"line_number":793,"context_line":"    cfg.IntOpt(\u0027num_pcie_ports\u0027,"},{"line_number":794,"context_line":"               default\u003d0,"},{"line_number":795,"context_line":"               min\u003d0,"},{"line_number":796,"context_line":"               max\u003d64,"},{"line_number":797,"context_line":"               help\u003d \"\"\""},{"line_number":798,"context_line":"The number of PCIe ports an instance will get."},{"line_number":799,"context_line":""}],"source_content_type":"text/x-python","patch_set":2,"id":"a3d22ed6_406e5fac","line":796,"range":{"start_line":796,"start_character":19,"end_line":796,"end_character":21},"in_reply_to":"19738f43_f67b7e47","updated":"2023-02-22 18:43:38.000000000","message":"that is not a bug its expected behvior.\n\nwe have a configu option to prevent you exceeding the maxiuym numbber of voluems as of stine\n\nhttps://specs.openstack.org/openstack/nova-specs/specs/stein/implemented/conf-max-attach-volumes.html\n\nand as part of that we enabeld you to have up to 720 disks\n\nhttps://github.com/openstack/nova/commit/36f310f469b91c7de72a8366c7d493e1e7a4fd0f\n\n\nif you need or want to uses more block devices  then the current pci count you should use hw_disk_bus\u003dscsi","commit_id":"ef7ffe066a10f57603478e886c5fec354cb471a3"},{"author":{"_account_id":7130,"name":"David Hill","email":"davidchill@hotmail.com","username":"dhill"},"change_message_id":"ad0b4c6fc22cc2e83bf9f6e8dedef0e8eac6a70a","unresolved":true,"context_lines":[{"line_number":793,"context_line":"    cfg.IntOpt(\u0027num_pcie_ports\u0027,"},{"line_number":794,"context_line":"               default\u003d0,"},{"line_number":795,"context_line":"               min\u003d0,"},{"line_number":796,"context_line":"               max\u003d64,"},{"line_number":797,"context_line":"               help\u003d \"\"\""},{"line_number":798,"context_line":"The number of PCIe ports an instance will get."},{"line_number":799,"context_line":""}],"source_content_type":"text/x-python","patch_set":2,"id":"8f01b41e_cecff8c9","line":796,"range":{"start_line":796,"start_character":19,"end_line":796,"end_character":21},"in_reply_to":"478db049_90ee8813","updated":"2023-02-22 18:01:08.000000000","message":"I think this might\u0027ve been a quick fix to an issue that could\u0027ve been fixed better by not limiting all architectures to the lowest number possible that works on all of them ... but if it requires a rework or a spec, so be it.","commit_id":"ef7ffe066a10f57603478e886c5fec354cb471a3"},{"author":{"_account_id":7130,"name":"David Hill","email":"davidchill@hotmail.com","username":"dhill"},"change_message_id":"ddf7a9c0f763901da8e4cfcf8b0e0b2d877fd3b3","unresolved":true,"context_lines":[{"line_number":793,"context_line":"    cfg.IntOpt(\u0027num_pcie_ports\u0027,"},{"line_number":794,"context_line":"               default\u003d0,"},{"line_number":795,"context_line":"               min\u003d0,"},{"line_number":796,"context_line":"               max\u003d64,"},{"line_number":797,"context_line":"               help\u003d \"\"\""},{"line_number":798,"context_line":"The number of PCIe ports an instance will get."},{"line_number":799,"context_line":""}],"source_content_type":"text/x-python","patch_set":2,"id":"aee950b0_796f6d45","line":796,"range":{"start_line":796,"start_character":19,"end_line":796,"end_character":21},"in_reply_to":"4f47ed0d_4b0c662d","updated":"2023-02-18 00:25:46.000000000","message":"```\nA PCI Express Root bus supports up to 32 devices. Since each\nPCI Express Root Port is a function and a multi-function\ndevice may support up to 8 functions, the maximum possible\nnumber of PCI Express Root Ports per PCI Express Root Bus is 256.\n```\n\nSo how could we reach 256 PCI express root ports ?  Add 32 devices with 8 functions each ?","commit_id":"ef7ffe066a10f57603478e886c5fec354cb471a3"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"89da2b164732d9d175d1211e448a931b4faad50c","unresolved":true,"context_lines":[{"line_number":793,"context_line":"    cfg.IntOpt(\u0027num_pcie_ports\u0027,"},{"line_number":794,"context_line":"               default\u003d0,"},{"line_number":795,"context_line":"               min\u003d0,"},{"line_number":796,"context_line":"               max\u003d64,"},{"line_number":797,"context_line":"               help\u003d \"\"\""},{"line_number":798,"context_line":"The number of PCIe ports an instance will get."},{"line_number":799,"context_line":""}],"source_content_type":"text/x-python","patch_set":2,"id":"96fd521c_eea049bc","line":796,"range":{"start_line":796,"start_character":19,"end_line":796,"end_character":21},"in_reply_to":"8f01b41e_cecff8c9","updated":"2023-02-22 18:14:19.000000000","message":"even as  aquick fix its still a feature and would not be backported.\n\nso if we are going to adresss this i would prefer to do it properly.","commit_id":"ef7ffe066a10f57603478e886c5fec354cb471a3"},{"author":{"_account_id":7130,"name":"David Hill","email":"davidchill@hotmail.com","username":"dhill"},"change_message_id":"cc8f9a582a2c1bc7295b23bddceafd8a90784f67","unresolved":true,"context_lines":[{"line_number":793,"context_line":"    cfg.IntOpt(\u0027num_pcie_ports\u0027,"},{"line_number":794,"context_line":"               default\u003d0,"},{"line_number":795,"context_line":"               min\u003d0,"},{"line_number":796,"context_line":"               max\u003d64,"},{"line_number":797,"context_line":"               help\u003d \"\"\""},{"line_number":798,"context_line":"The number of PCIe ports an instance will get."},{"line_number":799,"context_line":""}],"source_content_type":"text/x-python","patch_set":2,"id":"19738f43_f67b7e47","line":796,"range":{"start_line":796,"start_character":19,"end_line":796,"end_character":21},"in_reply_to":"96fd521c_eea049bc","updated":"2023-02-22 18:17:32.000000000","message":"Sure no worries but for some operators this will become a bug such as this:\n~~~\n2023-01-13 16:48:56.051 7 ERROR nova.virt.block_device [instance: 07120906-e3ea-4100-9f96-7180e20a1c62] libvirt.libvirtError: internal error: No more available PCI slots\n2023-01-13 16:48:56.051 7 ERROR nova.virt.block_device [instance: 07120906-e3ea-4100-9f96-7180e20a1c62]\n2023-01-13 16:48:59.260 7 ERROR nova.compute.manager [req-432b58ba-edda-4bf3-906b-e6d11070a196 ae7c2e975f91433cb47a08651fd2a91f ab83426af6b04f818ddc0b2615e9afe5 - default default] [instance: 07120906-e3ea-4100-9f96-7180e20a1c62] Failed to attach 4c799126-aaa7-49e3-be8b-f4590241ffe9 at /dev/vdaa: libvirt.libvirtError: internal error: No more available PCI slots\n~~~\nShould I open a nova bug ?","commit_id":"ef7ffe066a10f57603478e886c5fec354cb471a3"},{"author":{"_account_id":7130,"name":"David Hill","email":"davidchill@hotmail.com","username":"dhill"},"change_message_id":"ce0c51b2e931daa76479c994e43096b5b6f2af70","unresolved":true,"context_lines":[{"line_number":793,"context_line":"    cfg.IntOpt(\u0027num_pcie_ports\u0027,"},{"line_number":794,"context_line":"               default\u003d0,"},{"line_number":795,"context_line":"               min\u003d0,"},{"line_number":796,"context_line":"               max\u003d64,"},{"line_number":797,"context_line":"               help\u003d \"\"\""},{"line_number":798,"context_line":"The number of PCIe ports an instance will get."},{"line_number":799,"context_line":""}],"source_content_type":"text/x-python","patch_set":2,"id":"97f05a0d_b7347de4","line":796,"range":{"start_line":796,"start_character":19,"end_line":796,"end_character":21},"in_reply_to":"a3d22ed6_406e5fac","updated":"2023-06-05 15:24:27.000000000","message":"So we should abandon this change or we still want to increase it to 32 for x86_64 ?","commit_id":"ef7ffe066a10f57603478e886c5fec354cb471a3"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"bec278f02bafeccb635be88cccff093603e1d80d","unresolved":true,"context_lines":[{"line_number":793,"context_line":"    cfg.IntOpt(\u0027num_pcie_ports\u0027,"},{"line_number":794,"context_line":"               default\u003d0,"},{"line_number":795,"context_line":"               min\u003d0,"},{"line_number":796,"context_line":"               max\u003d64,"},{"line_number":797,"context_line":"               help\u003d \"\"\""},{"line_number":798,"context_line":"The number of PCIe ports an instance will get."},{"line_number":799,"context_line":""}],"source_content_type":"text/x-python","patch_set":2,"id":"478db049_90ee8813","line":796,"range":{"start_line":796,"start_character":19,"end_line":796,"end_character":21},"in_reply_to":"aee950b0_796f6d45","updated":"2023-02-20 11:02:56.000000000","message":"potentially yes however this is a feature not a bug so we would need to do this via a spec. i suspect that we would need to add pcie extention bridges to eatch fo the fucntions. ore create a complext topolgy.","commit_id":"ef7ffe066a10f57603478e886c5fec354cb471a3"}]}