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{"doc/admin-guide-cloud/source/compute-flavors.rst":[{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"1caeb5db87fa4c8fe5bb47468a2b02992d2bcc2e","unresolved":false,"context_lines":[{"line_number":362,"context_line":"    For the libvirt driver, you can pin the virtual CPUs (vCPUs) of instances"},{"line_number":363,"context_line":"    to the host\u0027s physical CPU cores (pCPUs) using properties. This will"},{"line_number":364,"context_line":"    result in improved instance determinism and performance. You can further"},{"line_number":365,"context_line":"    refine this by stating how hardware CPU \"threads\" (e.g. HyperThreads) be"},{"line_number":366,"context_line":"    used."},{"line_number":367,"context_line":""},{"line_number":368,"context_line":"    .. note::"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_bdab8dd5","line":365,"updated":"2016-02-16 21:23:14.000000000","message":"Eliminate \"e.g.\" per writing style guidelines http://docs.openstack.org/contributor-guide/writing-style/word-choice.html\n\nSuggest a revision like this, \"You can further refine vCPU pins by stating how hardware CPU threads, such as HyperThreads, be used.\"","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"8e0e57b1207de8a998e836f671f3feadd9ae8079","unresolved":false,"context_lines":[{"line_number":362,"context_line":"    For the libvirt driver, you can pin the virtual CPUs (vCPUs) of instances"},{"line_number":363,"context_line":"    to the host\u0027s physical CPU cores (pCPUs) using properties. This will"},{"line_number":364,"context_line":"    result in improved instance determinism and performance. You can further"},{"line_number":365,"context_line":"    refine this by stating how hardware CPU \"threads\" (e.g. HyperThreads) be"},{"line_number":366,"context_line":"    used."},{"line_number":367,"context_line":""},{"line_number":368,"context_line":"    .. note::"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_c26c92d2","line":365,"in_reply_to":"dae33548_bdab8dd5","updated":"2016-02-17 09:57:09.000000000","message":"Did it slightly differently that suggested. Also, HyperThreading is an widely used term, like \"FedEx\" for a courier, but it\u0027s technically a trademark. I used the full version just in case, but I don\u0027t know what the OpenStack guidelines are on copyrights/trademarks. Please suggest changes as necessary.","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"1caeb5db87fa4c8fe5bb47468a2b02992d2bcc2e","unresolved":false,"context_lines":[{"line_number":391,"context_line":""},{"line_number":392,"context_line":"    Valid CPU-THREAD-POLICY values are:"},{"line_number":393,"context_line":""},{"line_number":394,"context_line":"    - ``prefer``-(default) The host may or may not have an SMT architecture."},{"line_number":395,"context_line":"    - ``isolate``- The host must not have an SMT architecture, or must emulate"},{"line_number":396,"context_line":"      a non-SMT architecture. If the host does not have an SMT architecture,"},{"line_number":397,"context_line":"      each vCPU will simply be placed on a different core as expected. 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The dash prints differently in the output.","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"1caeb5db87fa4c8fe5bb47468a2b02992d2bcc2e","unresolved":false,"context_lines":[{"line_number":391,"context_line":""},{"line_number":392,"context_line":"    Valid CPU-THREAD-POLICY values are:"},{"line_number":393,"context_line":""},{"line_number":394,"context_line":"    - ``prefer``-(default) The host may or may not have an SMT architecture."},{"line_number":395,"context_line":"    - ``isolate``- The host must not have an SMT architecture, or must emulate"},{"line_number":396,"context_line":"      a non-SMT architecture. If the host does not have an SMT architecture,"},{"line_number":397,"context_line":"      each vCPU will simply be placed on a different core as expected. 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If the"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_7fdf210d","line":394,"range":{"start_line":394,"start_character":16,"end_line":394,"end_character":18},"in_reply_to":"dae33548_fde35531","updated":"2016-02-17 09:57:09.000000000","message":"I rebased this onto a commit that removed these unicode dashes (they don\u0027t display correctly in all terminals and they\u0027re not necessary)","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"1caeb5db87fa4c8fe5bb47468a2b02992d2bcc2e","unresolved":false,"context_lines":[{"line_number":394,"context_line":"    - ``prefer``-(default) The host may or may not have an SMT architecture."},{"line_number":395,"context_line":"    - ``isolate``- The host must not have an SMT architecture, or must emulate"},{"line_number":396,"context_line":"      a non-SMT architecture. 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As such,"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_7f060187","line":397,"range":{"start_line":397,"start_character":16,"end_line":397,"end_character":30},"in_reply_to":"dae33548_7d2aa52d","updated":"2016-02-17 09:57:09.000000000","message":"Done","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"1caeb5db87fa4c8fe5bb47468a2b02992d2bcc2e","unresolved":false,"context_lines":[{"line_number":395,"context_line":"    - ``isolate``- The host must not have an SMT architecture, or must emulate"},{"line_number":396,"context_line":"      a non-SMT architecture. If the host does not have an SMT architecture,"},{"line_number":397,"context_line":"      each vCPU will simply be placed on a different core as expected. If the"},{"line_number":398,"context_line":"      host does have an SMT architecture (i.e. one or more cores have \"thread"},{"line_number":399,"context_line":"      siblings\") then each vCPU will be placed on a different physical core"},{"line_number":400,"context_line":"      and no vCPUs from other guests will be placed on the same core. As such,"},{"line_number":401,"context_line":"      one thread sibling is always guaranteed to always be unused."}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_7db465d0","line":398,"range":{"start_line":398,"start_character":42,"end_line":398,"end_character":45},"updated":"2016-02-16 21:23:14.000000000","message":"replace with \"for example,\"","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"8e0e57b1207de8a998e836f671f3feadd9ae8079","unresolved":false,"context_lines":[{"line_number":395,"context_line":"    - ``isolate``- The host must not have an SMT architecture, or must emulate"},{"line_number":396,"context_line":"      a non-SMT architecture. If the host does not have an SMT architecture,"},{"line_number":397,"context_line":"      each vCPU will simply be placed on a different core as expected. If the"},{"line_number":398,"context_line":"      host does have an SMT architecture (i.e. one or more cores have \"thread"},{"line_number":399,"context_line":"      siblings\") then each vCPU will be placed on a different physical core"},{"line_number":400,"context_line":"      and no vCPUs from other guests will be placed on the same core. As such,"},{"line_number":401,"context_line":"      one thread sibling is always guaranteed to always be unused."}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_fffa1174","line":398,"range":{"start_line":398,"start_character":42,"end_line":398,"end_character":45},"in_reply_to":"dae33548_7db465d0","updated":"2016-02-17 09:57:09.000000000","message":"Done","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"1caeb5db87fa4c8fe5bb47468a2b02992d2bcc2e","unresolved":false,"context_lines":[{"line_number":396,"context_line":"      a non-SMT architecture. If the host does not have an SMT architecture,"},{"line_number":397,"context_line":"      each vCPU will simply be placed on a different core as expected. If the"},{"line_number":398,"context_line":"      host does have an SMT architecture (i.e. one or more cores have \"thread"},{"line_number":399,"context_line":"      siblings\") then each vCPU will be placed on a different physical core"},{"line_number":400,"context_line":"      and no vCPUs from other guests will be placed on the same core. As such,"},{"line_number":401,"context_line":"      one thread sibling is always guaranteed to always be unused."},{"line_number":402,"context_line":"    - ``require``- The host must have an SMT architecture. Each vCPU will be"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_1dfef936","line":399,"range":{"start_line":399,"start_character":15,"end_line":399,"end_character":46},"updated":"2016-02-16 21:23:14.000000000","message":"Suggest revision something like, \"...siblings\"), then each vCPU is placed on a different physical core. No vCPUs from other guests are placed on the same core.\"\n\nAdd a comma after the parenthetical statement. Change verb to present tense. Start a new sentence for the last phrase to keep both sentences short.","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"8e0e57b1207de8a998e836f671f3feadd9ae8079","unresolved":false,"context_lines":[{"line_number":396,"context_line":"      a non-SMT architecture. If the host does not have an SMT architecture,"},{"line_number":397,"context_line":"      each vCPU will simply be placed on a different core as expected. If the"},{"line_number":398,"context_line":"      host does have an SMT architecture (i.e. one or more cores have \"thread"},{"line_number":399,"context_line":"      siblings\") then each vCPU will be placed on a different physical core"},{"line_number":400,"context_line":"      and no vCPUs from other guests will be placed on the same core. As such,"},{"line_number":401,"context_line":"      one thread sibling is always guaranteed to always be unused."},{"line_number":402,"context_line":"    - ``require``- The host must have an SMT architecture. Each vCPU will be"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_5f805dc0","line":399,"range":{"start_line":399,"start_character":15,"end_line":399,"end_character":46},"in_reply_to":"dae33548_1dfef936","updated":"2016-02-17 09:57:09.000000000","message":"Done","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"1caeb5db87fa4c8fe5bb47468a2b02992d2bcc2e","unresolved":false,"context_lines":[{"line_number":398,"context_line":"      host does have an SMT architecture (i.e. one or more cores have \"thread"},{"line_number":399,"context_line":"      siblings\") then each vCPU will be placed on a different physical core"},{"line_number":400,"context_line":"      and no vCPUs from other guests will be placed on the same core. As such,"},{"line_number":401,"context_line":"      one thread sibling is always guaranteed to always be unused."},{"line_number":402,"context_line":"    - ``require``- The host must have an SMT architecture. Each vCPU will be"},{"line_number":403,"context_line":"      allocated on thread siblings. If the host does not have an SMT"},{"line_number":404,"context_line":"      architecture then it will not be used. If the host has an SMT"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_9db7a985","line":401,"range":{"start_line":401,"start_character":49,"end_line":401,"end_character":55},"updated":"2016-02-16 21:23:14.000000000","message":"eliminate this redundant instance of \"always\"\n\nInstead of saying \"unused\" could we replace it with \"available\"?","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"8e0e57b1207de8a998e836f671f3feadd9ae8079","unresolved":false,"context_lines":[{"line_number":398,"context_line":"      host does have an SMT architecture (i.e. one or more cores have \"thread"},{"line_number":399,"context_line":"      siblings\") then each vCPU will be placed on a different physical core"},{"line_number":400,"context_line":"      and no vCPUs from other guests will be placed on the same core. As such,"},{"line_number":401,"context_line":"      one thread sibling is always guaranteed to always be unused."},{"line_number":402,"context_line":"    - ``require``- The host must have an SMT architecture. Each vCPU will be"},{"line_number":403,"context_line":"      allocated on thread siblings. If the host does not have an SMT"},{"line_number":404,"context_line":"      architecture then it will not be used. If the host has an SMT"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_dfdaade7","line":401,"range":{"start_line":401,"start_character":49,"end_line":401,"end_character":55},"in_reply_to":"dae33548_9db7a985","updated":"2016-02-17 09:57:09.000000000","message":"unusable was more apt, seeing as no other instance can use this core","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"1caeb5db87fa4c8fe5bb47468a2b02992d2bcc2e","unresolved":false,"context_lines":[{"line_number":399,"context_line":"      siblings\") then each vCPU will be placed on a different physical core"},{"line_number":400,"context_line":"      and no vCPUs from other guests will be placed on the same core. As such,"},{"line_number":401,"context_line":"      one thread sibling is always guaranteed to always be unused."},{"line_number":402,"context_line":"    - ``require``- The host must have an SMT architecture. Each vCPU will be"},{"line_number":403,"context_line":"      allocated on thread siblings. If the host does not have an SMT"},{"line_number":404,"context_line":"      architecture then it will not be used. If the host has an SMT"},{"line_number":405,"context_line":"      architecture, but not enough cores with free thread siblings are"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_3d677d26","line":402,"range":{"start_line":402,"start_character":69,"end_line":402,"end_character":76},"updated":"2016-02-16 21:23:14.000000000","message":"replace with \"is\"","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"1caeb5db87fa4c8fe5bb47468a2b02992d2bcc2e","unresolved":false,"context_lines":[{"line_number":401,"context_line":"      one thread sibling is always guaranteed to always be unused."},{"line_number":402,"context_line":"    - ``require``- The host must have an SMT architecture. Each vCPU will be"},{"line_number":403,"context_line":"      allocated on thread siblings. If the host does not have an SMT"},{"line_number":404,"context_line":"      architecture then it will not be used. If the host has an SMT"},{"line_number":405,"context_line":"      architecture, but not enough cores with free thread siblings are"},{"line_number":406,"context_line":"      available, then scheduling will fail."},{"line_number":407,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_bd738de6","line":404,"range":{"start_line":404,"start_character":27,"end_line":404,"end_character":31},"updated":"2016-02-16 21:23:14.000000000","message":"replace with \"is\"","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"8e0e57b1207de8a998e836f671f3feadd9ae8079","unresolved":false,"context_lines":[{"line_number":401,"context_line":"      one thread sibling is always guaranteed to always be unused."},{"line_number":402,"context_line":"    - ``require``- The host must have an SMT architecture. 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If the host has an SMT"},{"line_number":405,"context_line":"      architecture, but not enough cores with free thread siblings are"},{"line_number":406,"context_line":"      available, then scheduling will fail."},{"line_number":407,"context_line":""}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_3fe479aa","line":404,"range":{"start_line":404,"start_character":27,"end_line":404,"end_character":31},"in_reply_to":"dae33548_bd738de6","updated":"2016-02-17 09:57:09.000000000","message":"Done","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"1caeb5db87fa4c8fe5bb47468a2b02992d2bcc2e","unresolved":false,"context_lines":[{"line_number":403,"context_line":"      allocated on thread siblings. If the host does not have an SMT"},{"line_number":404,"context_line":"      architecture then it will not be used. If the host has an SMT"},{"line_number":405,"context_line":"      architecture, but not enough cores with free thread siblings are"},{"line_number":406,"context_line":"      available, then scheduling will fail."},{"line_number":407,"context_line":""},{"line_number":408,"context_line":"Project private flavors"},{"line_number":409,"context_line":"    Flavors can also be assigned to particular projects. By default, a"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_3d35bdf6","line":406,"range":{"start_line":406,"start_character":33,"end_line":406,"end_character":42},"updated":"2016-02-16 21:23:14.000000000","message":"replace with \"fails\"","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"8e0e57b1207de8a998e836f671f3feadd9ae8079","unresolved":false,"context_lines":[{"line_number":403,"context_line":"      allocated on thread siblings. If the host does not have an SMT"},{"line_number":404,"context_line":"      architecture then it will not be used. If the host has an SMT"},{"line_number":405,"context_line":"      architecture, but not enough cores with free thread siblings are"},{"line_number":406,"context_line":"      available, then scheduling will fail."},{"line_number":407,"context_line":""},{"line_number":408,"context_line":"Project private flavors"},{"line_number":409,"context_line":"    Flavors can also be assigned to particular projects. By default, a"}],"source_content_type":"text/x-rst","patch_set":1,"id":"dae33548_22473e4c","line":406,"range":{"start_line":406,"start_character":33,"end_line":406,"end_character":42},"in_reply_to":"dae33548_3d35bdf6","updated":"2016-02-17 09:57:09.000000000","message":"Done","commit_id":"96f6f191ac33066465a9c0dec3ea7bd53615842b"},{"author":{"_account_id":19779,"name":"Chason Chan","display_name":"chenxing","email":"chason.chan@foxmail.com","username":"chenxing"},"change_message_id":"1f80f5502d5d5391b7e2beb3db8e6e4b621b9c48","unresolved":false,"context_lines":[{"line_number":364,"context_line":"CPU pinning policy"},{"line_number":365,"context_line":"    For the libvirt driver, you can pin the virtual CPUs (vCPUs) of instances"},{"line_number":366,"context_line":"    to the host\u0027s physical CPU cores (pCPUs) using properties. You can further"},{"line_number":367,"context_line":"    refine this by stating how hardware CPU \"threads\" in a a simultaneous"},{"line_number":368,"context_line":"    multithreading-based (SMT) architecture, for example an Intel processor"},{"line_number":369,"context_line":"    with Hyper-Threading technology, be used. These configurations will result"},{"line_number":370,"context_line":"    in improved per-instance determinism and performance."}],"source_content_type":"text/x-rst","patch_set":2,"id":"dae33548_0f120857","line":367,"range":{"start_line":367,"start_character":57,"end_line":367,"end_character":60},"updated":"2016-02-17 16:41:37.000000000","message":"remove a \"a\".","commit_id":"1874760e08bdf10585e75ed898868f23990419f8"},{"author":{"_account_id":19779,"name":"Chason Chan","display_name":"chenxing","email":"chason.chan@foxmail.com","username":"chenxing"},"change_message_id":"1f80f5502d5d5391b7e2beb3db8e6e4b621b9c48","unresolved":false,"context_lines":[{"line_number":369,"context_line":"    with Hyper-Threading technology, be used. These configurations will result"},{"line_number":370,"context_line":"    in improved per-instance determinism and performance."},{"line_number":371,"context_line":""},{"line_number":372,"context_line":"    .. note::"},{"line_number":373,"context_line":"        Host aggregates should be used to separate these \"pinned\" instances"},{"line_number":374,"context_line":"        from unpinned instances as the latter will not respect the resourcing"},{"line_number":375,"context_line":"        requirements of the former."},{"line_number":376,"context_line":""}],"source_content_type":"text/x-rst","patch_set":2,"id":"dae33548_2f7eec18","line":373,"range":{"start_line":372,"start_character":4,"end_line":373,"end_character":75},"updated":"2016-02-17 16:41:37.000000000","message":"need one blank line.","commit_id":"1874760e08bdf10585e75ed898868f23990419f8"},{"author":{"_account_id":10607,"name":"Alexandra Settle","email":"a.settle@outlook.com","username":"asettle"},"change_message_id":"f30efaa99942d32c672f69267d121dff4abb0a83","unresolved":false,"context_lines":[{"line_number":364,"context_line":"CPU pinning policy"},{"line_number":365,"context_line":"    For the libvirt driver, you can pin the virtual CPUs (vCPUs) of instances"},{"line_number":366,"context_line":"    to the host\u0027s physical CPU cores (pCPUs) using properties. You can further"},{"line_number":367,"context_line":"    refine this by stating how hardware CPU \"threads\" in a simultaneous"},{"line_number":368,"context_line":"    multithreading-based (SMT) architecture, for example an Intel processor"},{"line_number":369,"context_line":"    with Hyper-Threading technology, be used. These configurations will result"},{"line_number":370,"context_line":"    in improved per-instance determinism and performance."}],"source_content_type":"text/x-rst","patch_set":3,"id":"bae84128_081d2b0f","line":367,"updated":"2016-02-22 09:55:22.000000000","message":"Remove the scare quotes please :)","commit_id":"9452f1af20e5c0f2d92ec52b43cc5821bdf17374"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"3f9cdede2ed1542b16e685535dfc7c1ecc90dbab","unresolved":false,"context_lines":[{"line_number":364,"context_line":"CPU pinning policy"},{"line_number":365,"context_line":"    For the libvirt driver, you can pin the virtual CPUs (vCPUs) of instances"},{"line_number":366,"context_line":"    to the host\u0027s physical CPU cores (pCPUs) using properties. You can further"},{"line_number":367,"context_line":"    refine this by stating how hardware CPU \"threads\" in a simultaneous"},{"line_number":368,"context_line":"    multithreading-based (SMT) architecture, for example an Intel processor"},{"line_number":369,"context_line":"    with Hyper-Threading technology, be used. These configurations will result"},{"line_number":370,"context_line":"    in improved per-instance determinism and performance."}],"source_content_type":"text/x-rst","patch_set":3,"id":"bae84128_8a9648ee","line":367,"in_reply_to":"bae84128_081d2b0f","updated":"2016-02-22 13:31:55.000000000","message":"Done","commit_id":"9452f1af20e5c0f2d92ec52b43cc5821bdf17374"},{"author":{"_account_id":10607,"name":"Alexandra Settle","email":"a.settle@outlook.com","username":"asettle"},"change_message_id":"f30efaa99942d32c672f69267d121dff4abb0a83","unresolved":false,"context_lines":[{"line_number":365,"context_line":"    For the libvirt driver, you can pin the virtual CPUs (vCPUs) of instances"},{"line_number":366,"context_line":"    to the host\u0027s physical CPU cores (pCPUs) using properties. You can further"},{"line_number":367,"context_line":"    refine this by stating how hardware CPU \"threads\" in a simultaneous"},{"line_number":368,"context_line":"    multithreading-based (SMT) architecture, for example an Intel processor"},{"line_number":369,"context_line":"    with Hyper-Threading technology, be used. These configurations will result"},{"line_number":370,"context_line":"    in improved per-instance determinism and performance."},{"line_number":371,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"bae84128_08e40b0b","line":368,"updated":"2016-02-22 09:55:22.000000000","message":"architecture. For example an Intel...*","commit_id":"9452f1af20e5c0f2d92ec52b43cc5821bdf17374"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"3f9cdede2ed1542b16e685535dfc7c1ecc90dbab","unresolved":false,"context_lines":[{"line_number":365,"context_line":"    For the libvirt driver, you can pin the virtual CPUs (vCPUs) of instances"},{"line_number":366,"context_line":"    to the host\u0027s physical CPU cores (pCPUs) using properties. You can further"},{"line_number":367,"context_line":"    refine this by stating how hardware CPU \"threads\" in a simultaneous"},{"line_number":368,"context_line":"    multithreading-based (SMT) architecture, for example an Intel processor"},{"line_number":369,"context_line":"    with Hyper-Threading technology, be used. These configurations will result"},{"line_number":370,"context_line":"    in improved per-instance determinism and performance."},{"line_number":371,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"bae84128_ea08b42f","line":368,"in_reply_to":"bae84128_08e40b0b","updated":"2016-02-22 13:31:55.000000000","message":"This made sense as an aside, hence the splicing of sentences. This did make the sentence a tad bit long, however. Instead of splicing sentences, I have broken this section out into a proper rST \"aside\" and take the opportunity to expand on what \"thread siblings\" are. I\u0027ve tried to keep things in that aside as simple as possible while actually providing some helpful information, but let me know if it needs further work please :)","commit_id":"9452f1af20e5c0f2d92ec52b43cc5821bdf17374"},{"author":{"_account_id":10607,"name":"Alexandra Settle","email":"a.settle@outlook.com","username":"asettle"},"change_message_id":"f30efaa99942d32c672f69267d121dff4abb0a83","unresolved":false,"context_lines":[{"line_number":366,"context_line":"    to the host\u0027s physical CPU cores (pCPUs) using properties. You can further"},{"line_number":367,"context_line":"    refine this by stating how hardware CPU \"threads\" in a simultaneous"},{"line_number":368,"context_line":"    multithreading-based (SMT) architecture, for example an Intel processor"},{"line_number":369,"context_line":"    with Hyper-Threading technology, be used. These configurations will result"},{"line_number":370,"context_line":"    in improved per-instance determinism and performance."},{"line_number":371,"context_line":""},{"line_number":372,"context_line":"    .. note::"}],"source_content_type":"text/x-rst","patch_set":3,"id":"bae84128_a8bb5fe4","line":369,"updated":"2016-02-22 09:55:22.000000000","message":"Remove the sentence splicing here please. Separate this into two separate sentences - make it as clear and concise as possible please :)","commit_id":"9452f1af20e5c0f2d92ec52b43cc5821bdf17374"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"3f9cdede2ed1542b16e685535dfc7c1ecc90dbab","unresolved":false,"context_lines":[{"line_number":366,"context_line":"    to the host\u0027s physical CPU cores (pCPUs) using properties. You can further"},{"line_number":367,"context_line":"    refine this by stating how hardware CPU \"threads\" in a simultaneous"},{"line_number":368,"context_line":"    multithreading-based (SMT) architecture, for example an Intel processor"},{"line_number":369,"context_line":"    with Hyper-Threading technology, be used. These configurations will result"},{"line_number":370,"context_line":"    in improved per-instance determinism and performance."},{"line_number":371,"context_line":""},{"line_number":372,"context_line":"    .. note::"}],"source_content_type":"text/x-rst","patch_set":3,"id":"bae84128_4a08c02c","line":369,"in_reply_to":"bae84128_a8bb5fe4","updated":"2016-02-22 13:31:55.000000000","message":"See above","commit_id":"9452f1af20e5c0f2d92ec52b43cc5821bdf17374"},{"author":{"_account_id":10607,"name":"Alexandra Settle","email":"a.settle@outlook.com","username":"asettle"},"change_message_id":"f30efaa99942d32c672f69267d121dff4abb0a83","unresolved":false,"context_lines":[{"line_number":371,"context_line":""},{"line_number":372,"context_line":"    .. note::"},{"line_number":373,"context_line":""},{"line_number":374,"context_line":"        Host aggregates should be used to separate these \"pinned\" instances"},{"line_number":375,"context_line":"        from unpinned instances as the latter will not respect the resourcing"},{"line_number":376,"context_line":"        requirements of the former."},{"line_number":377,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"bae84128_c8b863e8","line":374,"updated":"2016-02-22 09:55:22.000000000","message":"Remove the scare quotes here too please","commit_id":"9452f1af20e5c0f2d92ec52b43cc5821bdf17374"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"3f9cdede2ed1542b16e685535dfc7c1ecc90dbab","unresolved":false,"context_lines":[{"line_number":371,"context_line":""},{"line_number":372,"context_line":"    .. note::"},{"line_number":373,"context_line":""},{"line_number":374,"context_line":"        Host aggregates should be used to separate these \"pinned\" instances"},{"line_number":375,"context_line":"        from unpinned instances as the latter will not respect the resourcing"},{"line_number":376,"context_line":"        requirements of the former."},{"line_number":377,"context_line":""}],"source_content_type":"text/x-rst","patch_set":3,"id":"bae84128_2a03bc10","line":374,"in_reply_to":"bae84128_c8b863e8","updated":"2016-02-22 13:31:55.000000000","message":"Done","commit_id":"9452f1af20e5c0f2d92ec52b43cc5821bdf17374"},{"author":{"_account_id":10607,"name":"Alexandra Settle","email":"a.settle@outlook.com","username":"asettle"},"change_message_id":"f30efaa99942d32c672f69267d121dff4abb0a83","unresolved":false,"context_lines":[{"line_number":401,"context_line":"       a non-SMT architecture. If the host does not have an SMT architecture,"},{"line_number":402,"context_line":"       each vCPU is placed on a different core as expected. If the host does"},{"line_number":403,"context_line":"       have an SMT architecture - that is, one or more cores have \"thread"},{"line_number":404,"context_line":"       siblings\" - then each vCPU is placed on a different physical core. No"},{"line_number":405,"context_line":"       vCPUs from other guests will be placed on the same core. As such, all"},{"line_number":406,"context_line":"       but one thread sibling on each utilized core is guaranteed to be"},{"line_number":407,"context_line":"       unusable."}],"source_content_type":"text/x-rst","patch_set":3,"id":"bae84128_88a5bbb6","line":404,"updated":"2016-02-22 09:55:22.000000000","message":"ditto remove","commit_id":"9452f1af20e5c0f2d92ec52b43cc5821bdf17374"},{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"3f9cdede2ed1542b16e685535dfc7c1ecc90dbab","unresolved":false,"context_lines":[{"line_number":401,"context_line":"       a non-SMT architecture. If the host does not have an SMT architecture,"},{"line_number":402,"context_line":"       each vCPU is placed on a different core as expected. If the host does"},{"line_number":403,"context_line":"       have an SMT architecture - that is, one or more cores have \"thread"},{"line_number":404,"context_line":"       siblings\" - then each vCPU is placed on a different physical core. No"},{"line_number":405,"context_line":"       vCPUs from other guests will be placed on the same core. As such, all"},{"line_number":406,"context_line":"       but one thread sibling on each utilized core is guaranteed to be"},{"line_number":407,"context_line":"       unusable."}],"source_content_type":"text/x-rst","patch_set":3,"id":"bae84128_8500f902","line":404,"in_reply_to":"bae84128_88a5bbb6","updated":"2016-02-22 13:31:55.000000000","message":"Done","commit_id":"9452f1af20e5c0f2d92ec52b43cc5821bdf17374"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"ba404e166eb2bae2bd77cfa8f09453effd948303","unresolved":false,"context_lines":[{"line_number":373,"context_line":"        SMT-based architectures include Intel processors with Hyper-Threading"},{"line_number":374,"context_line":"        technology. In these architectures, processor cores share a number of"},{"line_number":375,"context_line":"        components with one or more other cores. Cores in such architectures"},{"line_number":376,"context_line":"        are commonly refered to as hardware threads, while the cores that a"},{"line_number":377,"context_line":"        given core share components with are known as thread siblings."},{"line_number":378,"context_line":""},{"line_number":379,"context_line":"    .. note::"}],"source_content_type":"text/x-rst","patch_set":5,"id":"bae84128_253e348c","line":376,"range":{"start_line":376,"start_character":21,"end_line":376,"end_character":28},"updated":"2016-02-22 22:09:16.000000000","message":"According to the Contributor Guide, \"Use standard United States (U.S.) English throughout all technical publications.\"\n\nChange this instance to \"referred\"\n\nhttp://docs.openstack.org/contributor-guide/writing-style/general-writing-guidelines.html","commit_id":"d97ca7747092bc95efc99399eaf63efac3dee5d2"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"ba404e166eb2bae2bd77cfa8f09453effd948303","unresolved":false,"context_lines":[{"line_number":404,"context_line":"    Valid CPU-THREAD-POLICY values are:"},{"line_number":405,"context_line":""},{"line_number":406,"context_line":"    -  ``prefer``: (default) The host may or may not have an SMT architecture."},{"line_number":407,"context_line":"       Where an SMT architecture is present, thread siblings will be prefered."},{"line_number":408,"context_line":"    -  ``isolate``: The host must not have an SMT architecture or must emulate"},{"line_number":409,"context_line":"       a non-SMT architecture. If the host does not have an SMT architecture,"},{"line_number":410,"context_line":"       each vCPU is placed on a different core as expected. If the host does"}],"source_content_type":"text/x-rst","patch_set":5,"id":"bae84128_6512fc0a","line":407,"range":{"start_line":407,"start_character":60,"end_line":407,"end_character":78},"updated":"2016-02-22 22:09:16.000000000","message":"Replace with \"are preferred.\"\n\nThis makes the sentence use present tense and standard US English.","commit_id":"d97ca7747092bc95efc99399eaf63efac3dee5d2"},{"author":{"_account_id":14962,"name":"ologvinova","email":"ologvinova@mirantis.com","username":"ologvinova"},"change_message_id":"270b2d3bd047ffb0b052923d87f2af6682c13c1f","unresolved":false,"context_lines":[{"line_number":410,"context_line":"       each vCPU is placed on a different core as expected. If the host does"},{"line_number":411,"context_line":"       have an SMT architecture - that is, one or more cores have thread"},{"line_number":412,"context_line":"       siblings - then each vCPU is placed on a different physical core. No"},{"line_number":413,"context_line":"       vCPUs from other guests will be placed on the same core. Therefore all"},{"line_number":414,"context_line":"       but one thread sibling on each utilized core is guaranteed to be"},{"line_number":415,"context_line":"       unusable."},{"line_number":416,"context_line":"    -  ``require``: The host must have an SMT architecture. Each vCPU is"}],"source_content_type":"text/x-rst","patch_set":5,"id":"bae84128_f6e368a2","line":413,"range":{"start_line":413,"start_character":73,"end_line":413,"end_character":74},"updated":"2016-02-22 20:21:25.000000000","message":"A comma after \u0027Therefore\u0027 please.","commit_id":"d97ca7747092bc95efc99399eaf63efac3dee5d2"},{"author":{"_account_id":11482,"name":"Gudrun Wolfgram","email":"gmolson@us.ibm.com","username":"gmolson"},"change_message_id":"ba404e166eb2bae2bd77cfa8f09453effd948303","unresolved":false,"context_lines":[{"line_number":410,"context_line":"       each vCPU is placed on a different core as expected. If the host does"},{"line_number":411,"context_line":"       have an SMT architecture - that is, one or more cores have thread"},{"line_number":412,"context_line":"       siblings - then each vCPU is placed on a different physical core. No"},{"line_number":413,"context_line":"       vCPUs from other guests will be placed on the same core. Therefore all"},{"line_number":414,"context_line":"       but one thread sibling on each utilized core is guaranteed to be"},{"line_number":415,"context_line":"       unusable."},{"line_number":416,"context_line":"    -  ``require``: The host must have an SMT architecture. Each vCPU is"}],"source_content_type":"text/x-rst","patch_set":5,"id":"bae84128_45bc18dc","line":413,"range":{"start_line":413,"start_character":31,"end_line":413,"end_character":38},"updated":"2016-02-22 22:09:16.000000000","message":"replace with \"are\"","commit_id":"d97ca7747092bc95efc99399eaf63efac3dee5d2"},{"author":{"_account_id":10607,"name":"Alexandra Settle","email":"a.settle@outlook.com","username":"asettle"},"change_message_id":"2e3ccc6b80cc78e8657cdcae118dcd1251fac6da","unresolved":false,"context_lines":[{"line_number":410,"context_line":"       each vCPU is placed on a different core as expected. If the host does"},{"line_number":411,"context_line":"       have an SMT architecture - that is, one or more cores have thread"},{"line_number":412,"context_line":"       siblings - then each vCPU is placed on a different physical core. No"},{"line_number":413,"context_line":"       vCPUs from other guests will be placed on the same core. Therefore all"},{"line_number":414,"context_line":"       but one thread sibling on each utilized core is guaranteed to be"},{"line_number":415,"context_line":"       unusable."},{"line_number":416,"context_line":"    -  ``require``: The host must have an SMT architecture. Each vCPU is"}],"source_content_type":"text/x-rst","patch_set":5,"id":"bae84128_8e146aa0","line":413,"range":{"start_line":413,"start_character":31,"end_line":413,"end_character":38},"in_reply_to":"bae84128_45bc18dc","updated":"2016-02-23 10:45:19.000000000","message":"I\u0027d say you could completely remove \u0027therefore\u0027","commit_id":"d97ca7747092bc95efc99399eaf63efac3dee5d2"},{"author":{"_account_id":14962,"name":"ologvinova","email":"ologvinova@mirantis.com","username":"ologvinova"},"change_message_id":"270b2d3bd047ffb0b052923d87f2af6682c13c1f","unresolved":false,"context_lines":[{"line_number":415,"context_line":"       unusable."},{"line_number":416,"context_line":"    -  ``require``: The host must have an SMT architecture. Each vCPU is"},{"line_number":417,"context_line":"       allocated on thread siblings. If the host does not have an SMT"},{"line_number":418,"context_line":"       architecture then it is not used. If the host has an SMT architecture,"},{"line_number":419,"context_line":"       but not enough cores with free thread siblings are available, then"},{"line_number":420,"context_line":"       scheduling fails."}],"source_content_type":"text/x-rst","patch_set":5,"id":"bae84128_d61584e5","line":418,"range":{"start_line":418,"start_character":19,"end_line":418,"end_character":20},"updated":"2016-02-22 20:21:25.000000000","message":"A comma before \u0027then\u0027 please.","commit_id":"d97ca7747092bc95efc99399eaf63efac3dee5d2"}]}