)]}'
{"os_traits/__init__.py":[{"author":{"_account_id":11564,"name":"Chris Dent","email":"cdent@anticdent.org","username":"chdent"},"change_message_id":"9ffcb4e3b50017ebdfb4954c0866784d0f025902","unresolved":false,"context_lines":[{"line_number":29,"context_line":"from os_traits.hw.nic import accel  # noqa"},{"line_number":30,"context_line":"from os_traits.hw.nic import dcb  # noqa"},{"line_number":31,"context_line":"from os_traits.hw.nic import offload  # noqa"},{"line_number":32,"context_line":"from os_traits.hw.nic import sriov  # noqa"},{"line_number":33,"context_line":"from os_traits.storage import disk  # noqa"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":""}],"source_content_type":"text/x-python","patch_set":2,"id":"ffe62b97_4aab9c1c","line":32,"updated":"2017-03-24 17:52:47.000000000","message":"In my version, you only need to import the top of each tree here, each subtree is then responsible for importing its subtrees. Might save some noise. Not that it matters _that_ much.","commit_id":"92734bea1977d1d783a0defb0083af4b6f9fe140"}],"os_traits/hardware/nic.py":[{"author":{"_account_id":16688,"name":"Rodolfo Alonso","email":"ralonsoh@redhat.com","username":"rodolfo-alonso-hernandez"},"change_message_id":"65d95f271a32b1361edf1e6f284e91cfa5ec09ee","unresolved":false,"context_lines":[{"line_number":37,"context_line":""},{"line_number":38,"context_line":"# Hardware offloads supported by various NICs"},{"line_number":39,"context_line":"_NIC_OFFLOAD_NS \u003d _ROOT_NS + \u0027OFFLOAD_\u0027"},{"line_number":40,"context_line":""},{"line_number":41,"context_line":"HW_NIC_OFFLOAD_TSO \u003d _NIC_OFFLOAD_NS + \u0027TSO\u0027  # TCP segmentation"},{"line_number":42,"context_line":"HW_NIC_OFFLOAD_GRO \u003d _NIC_OFFLOAD_NS + \u0027GRO\u0027  # Generic receive"},{"line_number":43,"context_line":"HW_NIC_OFFLOAD_GSO \u003d _NIC_OFFLOAD_NS + \u0027GSO\u0027  # Generic segmentation"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffe62b97_d2ee5087","line":40,"updated":"2017-03-24 14:18:04.000000000","message":"New offload parameters to be added [1]:\n- rxhash: receive hashing\n- rdma: remote direct memory access\n- txudptnl: tx UDP tunnel segmentation\n\n[1] Supported in libvirt (https://libvirt.org/formatnode.html)","commit_id":"c7fb69e474fdd11b2c227371b55c7f35bdb4dfd8"},{"author":{"_account_id":7,"name":"Jay Pipes","email":"jaypipes@gmail.com","username":"jaypipes"},"change_message_id":"9a8d9ba949680a0b2c344ab9f482055ba3ec3c1d","unresolved":false,"context_lines":[{"line_number":37,"context_line":""},{"line_number":38,"context_line":"# Hardware offloads supported by various NICs"},{"line_number":39,"context_line":"_NIC_OFFLOAD_NS \u003d _ROOT_NS + \u0027OFFLOAD_\u0027"},{"line_number":40,"context_line":""},{"line_number":41,"context_line":"HW_NIC_OFFLOAD_TSO \u003d _NIC_OFFLOAD_NS + \u0027TSO\u0027  # TCP segmentation"},{"line_number":42,"context_line":"HW_NIC_OFFLOAD_GRO \u003d _NIC_OFFLOAD_NS + \u0027GRO\u0027  # Generic receive"},{"line_number":43,"context_line":"HW_NIC_OFFLOAD_GSO \u003d _NIC_OFFLOAD_NS + \u0027GSO\u0027  # Generic segmentation"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffe62b97_0a60f4a4","line":40,"in_reply_to":"ffe62b97_d2ee5087","updated":"2017-03-24 17:40:02.000000000","message":"Done","commit_id":"c7fb69e474fdd11b2c227371b55c7f35bdb4dfd8"},{"author":{"_account_id":16688,"name":"Rodolfo Alonso","email":"ralonsoh@redhat.com","username":"rodolfo-alonso-hernandez"},"change_message_id":"65d95f271a32b1361edf1e6f284e91cfa5ec09ee","unresolved":false,"context_lines":[{"line_number":49,"context_line":"HW_NIC_OFFLOAD_SCS \u003d _NIC_OFFLOAD_NS + \u0027SCS\u0027  # SCTP Checksum"},{"line_number":50,"context_line":"HW_NIC_OFFLOAD_L2CRC \u003d _NIC_OFFLOAD_NS + \u0027L2CRC\u0027  # Layer-2 CRC"},{"line_number":51,"context_line":"HW_NIC_OFFLOAD_FDF \u003d _NIC_OFFLOAD_NS + \u0027FDF\u0027  # Intel Flow-Director Filter"},{"line_number":52,"context_line":"HW_NIC_OFFLOAD_VLAN \u003d _NIC_OFFLOAD_NS + \u0027VLAN\u0027  # VLAN tag"},{"line_number":53,"context_line":"HW_NIC_OFFLOAD_VXLAN \u003d _NIC_OFFLOAD_NS + \u0027VXLAN\u0027  # VxLAN tunneling"},{"line_number":54,"context_line":"HW_NIC_OFFLOAD_GRE \u003d _NIC_OFFLOAD_NS + \u0027GRE\u0027  # GRE tunneling"},{"line_number":55,"context_line":"HW_NIC_OFFLOAD_GENEVE \u003d _NIC_OFFLOAD_NS + \u0027GENEVE\u0027  # Geneve tunneling"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffe62b97_929fa84f","line":52,"range":{"start_line":52,"start_character":0,"end_line":52,"end_character":58},"updated":"2017-03-24 14:18:04.000000000","message":"VLAN offload capability can be enabled in both directions.\n\nFor example, Libvirt [1] can discover both rxvlan and txvlan. This parameter should be splited in two.\n\n\n\n[1] https://libvirt.org/formatnode.html","commit_id":"c7fb69e474fdd11b2c227371b55c7f35bdb4dfd8"},{"author":{"_account_id":7,"name":"Jay Pipes","email":"jaypipes@gmail.com","username":"jaypipes"},"change_message_id":"9a8d9ba949680a0b2c344ab9f482055ba3ec3c1d","unresolved":false,"context_lines":[{"line_number":49,"context_line":"HW_NIC_OFFLOAD_SCS \u003d _NIC_OFFLOAD_NS + \u0027SCS\u0027  # SCTP Checksum"},{"line_number":50,"context_line":"HW_NIC_OFFLOAD_L2CRC \u003d _NIC_OFFLOAD_NS + \u0027L2CRC\u0027  # Layer-2 CRC"},{"line_number":51,"context_line":"HW_NIC_OFFLOAD_FDF \u003d _NIC_OFFLOAD_NS + \u0027FDF\u0027  # Intel Flow-Director Filter"},{"line_number":52,"context_line":"HW_NIC_OFFLOAD_VLAN \u003d _NIC_OFFLOAD_NS + \u0027VLAN\u0027  # VLAN tag"},{"line_number":53,"context_line":"HW_NIC_OFFLOAD_VXLAN \u003d _NIC_OFFLOAD_NS + \u0027VXLAN\u0027  # VxLAN tunneling"},{"line_number":54,"context_line":"HW_NIC_OFFLOAD_GRE \u003d _NIC_OFFLOAD_NS + \u0027GRE\u0027  # GRE tunneling"},{"line_number":55,"context_line":"HW_NIC_OFFLOAD_GENEVE \u003d _NIC_OFFLOAD_NS + \u0027GENEVE\u0027  # Geneve tunneling"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffe62b97_aaba28db","line":52,"range":{"start_line":52,"start_character":0,"end_line":52,"end_character":58},"in_reply_to":"ffe62b97_929fa84f","updated":"2017-03-24 17:40:02.000000000","message":"Done","commit_id":"c7fb69e474fdd11b2c227371b55c7f35bdb4dfd8"}],"os_traits/hw/nic/__init__.py":[{"author":{"_account_id":15334,"name":"Stephen Finucane","display_name":"stephenfin","email":"stephenfin@redhat.com","username":"sfinucan"},"change_message_id":"6dd42bd65e0c234b09d4b953f2cca3ba58230951","unresolved":false,"context_lines":[{"line_number":16,"context_line":""},{"line_number":17,"context_line":"register \u003d utils.register_fn(__name__)"},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"# A few generalized capabilities of some NICs"},{"line_number":20,"context_line":"register(\u0027SRIOV\u0027)  # NIC supports partitioning via SR-IOV"},{"line_number":21,"context_line":"register(\u0027MULTIQUEUE\u0027)  # \u003e1 receive and transmit queues"},{"line_number":22,"context_line":"register(\u0027VMDQ\u0027)  # Virtual machine device queues"},{"line_number":23,"context_line":"# Some NICs allow processing pipelines to be programmed via FPGAs embedded in"},{"line_number":24,"context_line":"# the NIC itself..."},{"line_number":25,"context_line":"register(\u0027PROGRAMMABLE_PIPELINE\u0027)"}],"source_content_type":"text/x-python","patch_set":3,"id":"ffe62b97_2375ac64","line":25,"range":{"start_line":19,"start_character":0,"end_line":25,"end_character":33},"updated":"2017-03-28 14:21:27.000000000","message":"These comments sound like something that should be a little more formalized, such that users could query them?","commit_id":"d8c4c98643d31226d4d345fd8cf4c1c26aef8dea"},{"author":{"_account_id":7,"name":"Jay Pipes","email":"jaypipes@gmail.com","username":"jaypipes"},"change_message_id":"f8db9902af8fb6eaa1631765ed3577b51b0c90c0","unresolved":false,"context_lines":[{"line_number":16,"context_line":""},{"line_number":17,"context_line":"register \u003d utils.register_fn(__name__)"},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"# A few generalized capabilities of some NICs"},{"line_number":20,"context_line":"register(\u0027SRIOV\u0027)  # NIC supports partitioning via SR-IOV"},{"line_number":21,"context_line":"register(\u0027MULTIQUEUE\u0027)  # \u003e1 receive and transmit queues"},{"line_number":22,"context_line":"register(\u0027VMDQ\u0027)  # Virtual machine device queues"},{"line_number":23,"context_line":"# Some NICs allow processing pipelines to be programmed via FPGAs embedded in"},{"line_number":24,"context_line":"# the NIC itself..."},{"line_number":25,"context_line":"register(\u0027PROGRAMMABLE_PIPELINE\u0027)"}],"source_content_type":"text/x-python","patch_set":3,"id":"ffe62b97_f57e5b17","line":25,"range":{"start_line":19,"start_character":0,"end_line":25,"end_character":33},"in_reply_to":"ffe62b97_2375ac64","updated":"2017-03-28 14:39:29.000000000","message":"Yeah, I\u0027d thought of that. Long term, we could add a description field to the Trait model in placement API and consider adding these comments as descriptions.","commit_id":"d8c4c98643d31226d4d345fd8cf4c1c26aef8dea"}],"os_traits/hw/nic/sriov.py":[{"author":{"_account_id":8802,"name":"Vladik Romanovsky","email":"vromanso@redhat.com","username":"vladikr"},"change_message_id":"fe2cd769cad0bd31638bc44c3e34593291e98e5b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"7ffa3b31_64d8731d","line":26,"updated":"2017-04-19 21:21:16.000000000","message":"VFs can also be \"trusted\" but it\u0027s PF.\n\"Trusted VFs\" can perform privileged operations, such as setting a custom mac and enter promiscuous mode. [1][2]\n\nAlso, perhaps it should state the function (virtual/physical)?\n\n[1]http://lists.osuosl.org/pipermail/intel-wired-lan/Week-of-Mon-20151005/002134.html\n[2]http://lxr.free-electrons.com/source/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c#L895","commit_id":"f9f5e2bd3584b0d09ca163bb2b9c1163e40c2211"},{"author":{"_account_id":7,"name":"Jay Pipes","email":"jaypipes@gmail.com","username":"jaypipes"},"change_message_id":"7223c509fbf9d132f8301b55d099c10c6d78f34e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"7ffa3b31_7f6800b8","line":26,"in_reply_to":"7ffa3b31_64d8731d","updated":"2017-04-19 21:47:31.000000000","message":"@vladikr: thx much for the review! What precisely do you mean by \"perhaps it should state the function (virtual/physical)\"?\n\nThe above traits are indicating the capabilities of the *physical function*. In other words, \"VF_QOS_TX\" would be assigned to the resource provider record of the physical function (which is the provider of SRIOV_NET_VF resources). The \"VF_QOS_TX\" trait would indicate that VFs on that PF would be able to restrict transmit rates separately.\n\nI wasn\u0027t planning on allowing VFs to be resource providers (and thus allowing traits to be associated to them). Only PFs would be resource providers and have these traits associated with them.\n\nPerhaps I need to reconsider that?","commit_id":"f9f5e2bd3584b0d09ca163bb2b9c1163e40c2211"},{"author":{"_account_id":8802,"name":"Vladik Romanovsky","email":"vromanso@redhat.com","username":"vladikr"},"change_message_id":"eb617691fea2820f7bac79f9fe5fc66fa1bd8065","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"7ffa3b31_bc3d73c5","line":26,"in_reply_to":"7ffa3b31_7f6800b8","updated":"2017-04-19 23:08:03.000000000","message":"Thanks for the clarification, Jay.\n\nI probably misunderstood the concept. I thought traits are needed for a selection of VFs and/or PFs. That\u0027s why I asked about the function (virtual/physical).\n\nThe \"Trusted\" option is a per VF setting, not sure how can it be represented here.\n\nProbably unrelated, but how a relation of PCI device to a NUMA node would be represented?","commit_id":"f9f5e2bd3584b0d09ca163bb2b9c1163e40c2211"},{"author":{"_account_id":8802,"name":"Vladik Romanovsky","email":"vromanso@redhat.com","username":"vladikr"},"change_message_id":"345377795c5a546f6362aa3ea327a9f278007f02","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"7ffa3b31_5ce1cf29","line":26,"in_reply_to":"7ffa3b31_bc3d73c5","updated":"2017-04-19 23:16:25.000000000","message":"Sorry, on the other hand, TX/RX Rate Limits are per VF setting as well, so it should be the same as with the trusted option.","commit_id":"f9f5e2bd3584b0d09ca163bb2b9c1163e40c2211"}],"os_traits/tests/test_os_traits.py":[{"author":{"_account_id":7166,"name":"Sylvain Bauza","email":"sbauza@redhat.com","username":"sbauza"},"change_message_id":"650a228b7949a71867edc567a6256a4771ad7a72","unresolved":false,"context_lines":[{"line_number":42,"context_line":"        self.assertIn(\"HW_CPU_X86_SSE42\", traits)"},{"line_number":43,"context_line":"        self.assertIn(ot.HW_CPU_X86_AVX2, traits)"},{"line_number":44,"context_line":"        self.assertNotIn(ot.STORAGE_DISK_SSD, traits)"},{"line_number":45,"context_line":"        self.assertNotIn(ot.HW_NIC_SRIOV, traits)"},{"line_number":46,"context_line":""},{"line_number":47,"context_line":"    def test_check_traits(self):"},{"line_number":48,"context_line":"        traits \u003d set([\"HW_CPU_X86_SSE42\", \"HW_CPU_X86_XOP\"])"}],"source_content_type":"text/x-python","patch_set":3,"id":"dfeb2761_ca17d2ed","line":45,"updated":"2017-03-30 21:17:49.000000000","message":"very small coverage but okay","commit_id":"d8c4c98643d31226d4d345fd8cf4c1c26aef8dea"}]}