)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"d6f0a629d65c595287ce2934864f7f3c5d3438d1","unresolved":false,"context_lines":[{"line_number":19,"context_line":"    - hw/cpu/x86/amd.py  -- AMD-only traits."},{"line_number":20,"context_line":"    - hw/cpu/x86/intel.py  -- Intel-only traits."},{"line_number":21,"context_line":"    - hw/cpu/x86/__init__.py  -- Common for both AMD and Intel."},{"line_number":22,"context_line":"    - hw/cpu/x86.py -- Deprecate the contents of this file with a"},{"line_number":23,"context_line":"      comment; and copy them into x86/__init__.py, which is its new"},{"line_number":24,"context_line":"      location."},{"line_number":25,"context_line":"    - hw/cpu/amd.py -- Deprecate the contents of this file with a"},{"line_number":26,"context_line":"      comment; and copy them into hw/cpu/x86/amd.py, which is its new"},{"line_number":27,"context_line":"      location."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":5,"id":"bfb3d3c7_1ac0f729","line":24,"range":{"start_line":22,"start_character":6,"end_line":24,"end_character":15},"updated":"2019-05-28 18:22:14.000000000","message":"Maybe provide or link to some justification or background for this change?  I remember Sean disliking the approach of putting anything substantial in __init__.py files. Although I\u0027m not religious about it, aesthetically I\u0027m more in his camp too.  Are there hard reasons for deprecating x86.py, or is it more of a style thing?  Given the downsides introduced by a deprecation causing the new and old ways to co-exist, I\u0027m hoping it\u0027s the former.  I expect that this was already explained somewhere in the various debates - sorry if I missed that, but anyway it would be useful to have it documented here for posterity and easier discoverability.","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"2e63f93b8f1ed8d52aedaa2ef689ffdf7f7417e1","unresolved":false,"context_lines":[{"line_number":19,"context_line":"    - hw/cpu/x86/amd.py  -- AMD-only traits."},{"line_number":20,"context_line":"    - hw/cpu/x86/intel.py  -- Intel-only traits."},{"line_number":21,"context_line":"    - hw/cpu/x86/__init__.py  -- Common for both AMD and Intel."},{"line_number":22,"context_line":"    - hw/cpu/x86.py -- Deprecate the contents of this file with a"},{"line_number":23,"context_line":"      comment; and copy them into x86/__init__.py, which is its new"},{"line_number":24,"context_line":"      location."},{"line_number":25,"context_line":"    - hw/cpu/amd.py -- Deprecate the contents of this file with a"},{"line_number":26,"context_line":"      comment; and copy them into hw/cpu/x86/amd.py, which is its new"},{"line_number":27,"context_line":"      location."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":5,"id":"bfb3d3c7_5bd991f0","line":24,"range":{"start_line":22,"start_character":6,"end_line":24,"end_character":15},"in_reply_to":"bfb3d3c7_1ac0f729","updated":"2019-05-28 21:45:20.000000000","message":"See comment in x86.py, there\u0027s no reason to keep the file as long as the string trait names that come out of the other end are preserved - which they are by including the same values in x86/__init__.py.\n\n \u003e Maybe provide or link to some justification or background for this\n \u003e change? I remember Sean disliking the approach of putting anything\n \u003e substantial in __init__.py files.\n\nIt\u0027s to maintain consistency with the way it\u0027s done throughout this repository. Not sure that needs to be justified, but feel free to include it here if you like.\n\n \u003e Given the\n \u003e downsides introduced by a deprecation causing the new and old ways\n \u003e to co-exist\n\nThere are no downsides and no deprecation. I think this (preservation of x86.py the file) is being confused with preservation of traits that are being \"renamed\" (moved to arch-specific namespaces). The old trait *names* must be preserved (because it\u0027s policy, and for the sanity of the placement database), but it matters not at all where the strings come from.\n\nLike, I could release an os-traits where I blew away the compute/, hw/, misc/, and storage/ subdirectories and put strings \u0027COMPUTE_DEVICE_TAGGING\u0027 through \u0027STORAGE_DISK_SSD\u0027 into os_traits.__init__.py. The world would tick along just fine.\n\nWhich isn\u0027t a half bad idea, as I\u0027m really not sure what this hierarchy of directories has ever bought us.","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":11564,"name":"Chris Dent","email":"cdent@anticdent.org","username":"chdent"},"change_message_id":"cbde63d4485f7469da73a2dcae4369e80c310bc7","unresolved":false,"context_lines":[{"line_number":19,"context_line":"    - hw/cpu/x86/amd.py  -- AMD-only traits."},{"line_number":20,"context_line":"    - hw/cpu/x86/intel.py  -- Intel-only traits."},{"line_number":21,"context_line":"    - hw/cpu/x86/__init__.py  -- Common for both AMD and Intel."},{"line_number":22,"context_line":"    - hw/cpu/x86.py -- Deprecate the contents of this file with a"},{"line_number":23,"context_line":"      comment; and copy them into x86/__init__.py, which is its new"},{"line_number":24,"context_line":"      location."},{"line_number":25,"context_line":"    - hw/cpu/amd.py -- Deprecate the contents of this file with a"},{"line_number":26,"context_line":"      comment; and copy them into hw/cpu/x86/amd.py, which is its new"},{"line_number":27,"context_line":"      location."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":5,"id":"bfb3d3c7_e0e8ca7c","line":24,"range":{"start_line":22,"start_character":6,"end_line":24,"end_character":15},"in_reply_to":"bfb3d3c7_5bd991f0","updated":"2019-05-29 10:09:46.000000000","message":"\u003e Like, I could release an os-traits where I blew away the compute/,\n \u003e hw/, misc/, and storage/ subdirectories and put strings\n \u003e \u0027COMPUTE_DEVICE_TAGGING\u0027 through \u0027STORAGE_DISK_SSD\u0027 into\n \u003e os_traits.__init__.py. The world would tick along just fine.\n \u003e \n \u003e Which isn\u0027t a half bad idea, as I\u0027m really not sure what this\n \u003e hierarchy of directories has ever bought us.\n\nThat could perhaps break compatibility. The symbols are accessible in two ways:\n\n    \u003e\u003e\u003e ot.hw.cpu.x86.amd.SEV\n    \u0027HW_CPU_X86_AMD_SEV\u0027\n    \u003e\u003e\u003e ot.HW_CPU_X86_AMD_SEV\n    \u0027HW_CPU_X86_AMD_SEV\u0027\n\nI can\u0027t find any evidence in placement or nova that they are ever used in the first way, but they are in tests (see test_os_traits.py for example).\n\nIt was done in https://review.opendev.org/#/c/448282/\n\nSo: I reckon we shouldn\u0027t break that or at least be sure we\u0027re aware of what we are doing if/when we do.","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"50b9c1007fa1f95e13ee755c3e32b1729cdceebe","unresolved":false,"context_lines":[{"line_number":19,"context_line":"    - hw/cpu/x86/amd.py  -- AMD-only traits."},{"line_number":20,"context_line":"    - hw/cpu/x86/intel.py  -- Intel-only traits."},{"line_number":21,"context_line":"    - hw/cpu/x86/__init__.py  -- Common for both AMD and Intel."},{"line_number":22,"context_line":"    - hw/cpu/x86.py -- Deprecate the contents of this file with a"},{"line_number":23,"context_line":"      comment; and copy them into x86/__init__.py, which is its new"},{"line_number":24,"context_line":"      location."},{"line_number":25,"context_line":"    - hw/cpu/amd.py -- Deprecate the contents of this file with a"},{"line_number":26,"context_line":"      comment; and copy them into hw/cpu/x86/amd.py, which is its new"},{"line_number":27,"context_line":"      location."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":5,"id":"bfb3d3c7_4d02383f","line":24,"range":{"start_line":22,"start_character":6,"end_line":24,"end_character":15},"in_reply_to":"bfb3d3c7_5bd991f0","updated":"2019-05-28 23:11:35.000000000","message":"\u003e See comment in x86.py, there\u0027s no reason to keep the file as long as the string trait names that come out of the other end are preserved - which they are by including the same values in x86/__init__.py.\n\nWell this is the bit I don\u0027t get - if that\u0027s true, why is the file still here in this patchset?\n\n[reads ahead ...]  OK, you are saying the same thing - that\u0027s good, it seems we agree :)\n\n \u003e \u003e Maybe provide or link to some justification or background for this change? I remember Sean disliking the approach of putting anything substantial in __init__.py files.\n \u003e \n \u003e It\u0027s to maintain consistency with the way it\u0027s done throughout this repository. Not sure that needs to be justified, but feel free to include it here if you like.\n\nIMHO consistency is sufficient justification in itself, but that doesn\u0027t make it self-evident.  A newbie such as me isn\u0027t (well, wasn\u0027t) yet familiar enough with the code to know that this way is more consistent.  Although I\u0027m not suggesting every commit message should be written with newbies as the principal audience - the line needs to be drawn somewhere :)\n\n \u003e \u003e Given the downsides introduced by a deprecation causing the new and old ways to co-exist\n \u003e \n \u003e There are no downsides and no deprecation.\n\nThere are in this patchset :-)  But yeah, I think we both agree that there doesn\u0027t need to be.\n\n \u003e I think this (preservation of x86.py the file) is being confused with preservation of traits that are being \"renamed\" (moved to arch-specific namespaces). The old trait *names* must be preserved (because it\u0027s policy, and for the sanity of the placement database), but it matters not at all where the strings come from.\n\nExactly. I was confused by the bit of the commit message which said \"Deprecate the contents of this file with a comment; and copy them into x86/__init__.py, which is its new location.\"  Here the operative word was \"copy\".  Like you I think that should have been \"move\".\n\n \u003e Like, I could release an os-traits where I blew away the compute/, hw/, misc/, and storage/ subdirectories and put strings \u0027COMPUTE_DEVICE_TAGGING\u0027 through \u0027STORAGE_DISK_SSD\u0027 into os_traits.__init__.py. The world would tick along just fine.\n\nYup.\n\n \u003e Which isn\u0027t a half bad idea, as I\u0027m really not sure what this hierarchy of directories has ever bought us.\n\nI\u0027m pretty sure that was actually proposed by someone in IRC during the debate.  I guess it would be OK, but personally in general I\u0027m a fan of smaller files (just like I\u0027m a fan of smaller methods ;-)","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"574b71d83801ab6ba708096039a21f1a6e6b09b1","unresolved":false,"context_lines":[{"line_number":19,"context_line":"    - hw/cpu/x86/amd.py  -- AMD-only traits."},{"line_number":20,"context_line":"    - hw/cpu/x86/intel.py  -- Intel-only traits."},{"line_number":21,"context_line":"    - hw/cpu/x86/__init__.py  -- Common for both AMD and Intel."},{"line_number":22,"context_line":"    - hw/cpu/x86.py -- Deprecate the contents of this file with a"},{"line_number":23,"context_line":"      comment; and copy them into x86/__init__.py, which is its new"},{"line_number":24,"context_line":"      location."},{"line_number":25,"context_line":"    - hw/cpu/amd.py -- Deprecate the contents of this file with a"},{"line_number":26,"context_line":"      comment; and copy them into hw/cpu/x86/amd.py, which is its new"},{"line_number":27,"context_line":"      location."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":5,"id":"bfb3d3c7_a315fc41","line":24,"range":{"start_line":22,"start_character":6,"end_line":24,"end_character":15},"in_reply_to":"bfb3d3c7_e0e8ca7c","updated":"2019-05-29 10:26:32.000000000","message":"\u003e That could perhaps break compatibility. The symbols are accessible\n \u003e in two ways:\n \u003e \n \u003e \u003e\u003e\u003e ot.hw.cpu.x86.amd.SEV\n \u003e \u0027HW_CPU_X86_AMD_SEV\u0027\n \u003e \u003e\u003e\u003e ot.HW_CPU_X86_AMD_SEV\n \u003e \u0027HW_CPU_X86_AMD_SEV\u0027\n\nAw, f, really? /me rage quits.\n\nBut that doesn\u0027t stop us from removing the x86.py module, right?","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"698fdb6640ad50cc798941c12c1301fe0c3d1b40","unresolved":false,"context_lines":[{"line_number":24,"context_line":""},{"line_number":25,"context_line":"    - hw/cpu/x86.py -- Two things: (a) move the contents of this file"},{"line_number":26,"context_line":"      into x86/__init__.py, which is its new location; this move"},{"line_number":27,"context_line":"      preserves the integrity of the string trait names as they were"},{"line_number":28,"context_line":"      before; and (b) given point (a), remove the now no longer needed"},{"line_number":29,"context_line":"      hw/cpu/x86.py.  (Justification: We are removing this file to"},{"line_number":30,"context_line":"      maintain consistency with the way it\u0027s done througout the"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":6,"id":"bfb3d3c7_d6e9c1e5","line":27,"range":{"start_line":27,"start_character":37,"end_line":27,"end_character":55},"updated":"2019-05-29 19:48:53.000000000","message":"and the python paths, as Chris mentioned","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"698fdb6640ad50cc798941c12c1301fe0c3d1b40","unresolved":false,"context_lines":[{"line_number":51,"context_line":"(*) Add various missing CPU flags to x86/intel.py, x86/amd.py and to"},{"line_number":52,"context_line":"    x86/__intel__.py."},{"line_number":53,"context_line":""},{"line_number":54,"context_line":"(*) Copy, and deprecate with a comment, flags from cpu/x86.py, e.g."},{"line_number":55,"context_line":"    \"VMX\" (Intel) and \"SVM\" (AMD), into corresponding vendor-specific"},{"line_number":56,"context_line":"    files."},{"line_number":57,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":6,"id":"bfb3d3c7_f6cde584","line":54,"range":{"start_line":54,"start_character":63,"end_line":54,"end_character":67},"updated":"2019-05-29 19:48:53.000000000","message":"i.e.","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"886997ff16fd3629abdadb8bf8b653fdc4fc7ca3","unresolved":false,"context_lines":[{"line_number":51,"context_line":"(*) Add various missing CPU flags to x86/intel.py, x86/amd.py and to"},{"line_number":52,"context_line":"    x86/__intel__.py."},{"line_number":53,"context_line":""},{"line_number":54,"context_line":"(*) Copy, and deprecate with a comment, flags from cpu/x86.py, e.g."},{"line_number":55,"context_line":"    \"VMX\" (Intel) and \"SVM\" (AMD), into corresponding vendor-specific"},{"line_number":56,"context_line":"    files."},{"line_number":57,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":6,"id":"bfb3d3c7_31baa76d","line":54,"range":{"start_line":54,"start_character":63,"end_line":54,"end_character":67},"in_reply_to":"bfb3d3c7_f6cde584","updated":"2019-05-29 20:54:58.000000000","message":"Will fix. :-)  It\u0027s a logical mistake; not even \"pedantry\".","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"698fdb6640ad50cc798941c12c1301fe0c3d1b40","unresolved":false,"context_lines":[{"line_number":66,"context_line":"[2] Thread conclusion:"},{"line_number":67,"context_line":"    http://lists.openstack.org/pipermail/openstack-discuss/2019-May/006364.html"},{"line_number":68,"context_line":""},{"line_number":69,"context_line":"Closes-Bug: #1830948"},{"line_number":70,"context_line":"Change-Id: I1c9a72d19ef9dadfb931efa3894867099974bcc7"},{"line_number":71,"context_line":"Signed-off-by: Kashyap Chamarthy \u003ckchamart@redhat.com\u003e"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":6,"id":"bfb3d3c7_56e071cd","line":69,"range":{"start_line":69,"start_character":13,"end_line":69,"end_character":20},"updated":"2019-05-29 19:48:53.000000000","message":"Why did you open a bug, out of curiosity?","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"3d6554b3877984f2aa2e9c05ef577e3426c62f2e","unresolved":false,"context_lines":[{"line_number":66,"context_line":"[2] Thread conclusion:"},{"line_number":67,"context_line":"    http://lists.openstack.org/pipermail/openstack-discuss/2019-May/006364.html"},{"line_number":68,"context_line":""},{"line_number":69,"context_line":"Closes-Bug: #1830948"},{"line_number":70,"context_line":"Change-Id: I1c9a72d19ef9dadfb931efa3894867099974bcc7"},{"line_number":71,"context_line":"Signed-off-by: Kashyap Chamarthy \u003ckchamart@redhat.com\u003e"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":6,"id":"9fb8cfa7_87f2069a","line":69,"range":{"start_line":69,"start_character":13,"end_line":69,"end_character":20},"in_reply_to":"bfb3d3c7_512e3bfb","updated":"2019-05-31 16:10:20.000000000","message":"I don\u0027t care, was just curious. Not like this is going to be backported or anything.","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"886997ff16fd3629abdadb8bf8b653fdc4fc7ca3","unresolved":false,"context_lines":[{"line_number":66,"context_line":"[2] Thread conclusion:"},{"line_number":67,"context_line":"    http://lists.openstack.org/pipermail/openstack-discuss/2019-May/006364.html"},{"line_number":68,"context_line":""},{"line_number":69,"context_line":"Closes-Bug: #1830948"},{"line_number":70,"context_line":"Change-Id: I1c9a72d19ef9dadfb931efa3894867099974bcc7"},{"line_number":71,"context_line":"Signed-off-by: Kashyap Chamarthy \u003ckchamart@redhat.com\u003e"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":6,"id":"bfb3d3c7_512e3bfb","line":69,"range":{"start_line":69,"start_character":13,"end_line":69,"end_character":20},"in_reply_to":"bfb3d3c7_56e071cd","updated":"2019-05-29 20:54:58.000000000","message":"Lame reason: Was asked to file it for downstream paperwork (I guess to map a downstream bug tracker to its corresponding upstream tracker).  If you want me to nix it, happy to drop it; I don\u0027t particularly care about it.","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"}],"os_traits/hw/cpu/amd.py":[{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"d19af29f4497c3f68333b83f9f2fd14303716a70","unresolved":false,"context_lines":[{"line_number":16,"context_line":"TRAITS \u003d ["},{"line_number":17,"context_line":"    # ref: https://developer.amd.com/sev/"},{"line_number":18,"context_line":"    \u0027SEV\u0027,"},{"line_number":19,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":20,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":21,"context_line":"    \u0027IBPB\u0027,"},{"line_number":22,"context_line":"    \u0027VIRT_SSBD\u0027,"}],"source_content_type":"text/x-python","patch_set":2,"id":"ffb9cba7_0336b9e7","line":19,"range":{"start_line":19,"start_character":11,"end_line":19,"end_character":78},"updated":"2019-04-24 15:43:21.000000000","message":"Is stibp [1] omitted on purpose?\n\n(Later) Seems common to Intel and AMD, so it should probably go in hw/cpu/x86?\n\n(Later later) Hm, I wonder if amd should have gone under x86 in the first place. Oh well, that ship has sailed.\n\n[1] https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi#l272","commit_id":"a26766a5c80411b478360797adef2d25e4f79ec2"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"39549c47863ec482a3dd04af5662620f1ea888b0","unresolved":false,"context_lines":[{"line_number":16,"context_line":"TRAITS \u003d ["},{"line_number":17,"context_line":"    # ref: https://developer.amd.com/sev/"},{"line_number":18,"context_line":"    \u0027SEV\u0027,"},{"line_number":19,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":20,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":21,"context_line":"    \u0027IBPB\u0027,"},{"line_number":22,"context_line":"    \u0027VIRT_SSBD\u0027,"}],"source_content_type":"text/x-python","patch_set":2,"id":"ffb9cba7_b1e60944","line":19,"range":{"start_line":19,"start_character":11,"end_line":19,"end_character":78},"in_reply_to":"ffb9cba7_0336b9e7","updated":"2019-04-25 09:08:11.000000000","message":"Eagle eyes.\n\nDidn\u0027t omit \u0027stibp\u0027 on purpose, accidental (as it wasn\u0027t in the HTML-rendered docs).  Thanks for catching that.\n\nAnd yes, as you noticed, it is common for both AMD and Intel; so I should add it on both places?","commit_id":"a26766a5c80411b478360797adef2d25e4f79ec2"},{"author":{"_account_id":1063,"name":"Ed Leafe","email":"ed@leafe.com","username":"ed-leafe"},"change_message_id":"d9d95160055f9ab19607bb74633f76c5a598dd83","unresolved":false,"context_lines":[{"line_number":16,"context_line":"TRAITS \u003d ["},{"line_number":17,"context_line":"    # ref: https://developer.amd.com/sev/"},{"line_number":18,"context_line":"    \u0027SEV\u0027,"},{"line_number":19,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":20,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":21,"context_line":"    \u0027IBPB\u0027,"},{"line_number":22,"context_line":"    \u0027VIRT_SSBD\u0027,"}],"source_content_type":"text/x-python","patch_set":2,"id":"ffb9cba7_911d02bf","line":19,"range":{"start_line":19,"start_character":11,"end_line":19,"end_character":78},"in_reply_to":"ffb9cba7_b1e60944","updated":"2019-04-25 12:55:45.000000000","message":"Would it be something in common with *all* CPUs, and could go in hw/cpu.py? If not, then it should be in each of the sub-types of CPU where it applies.","commit_id":"a26766a5c80411b478360797adef2d25e4f79ec2"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"d19af29f4497c3f68333b83f9f2fd14303716a70","unresolved":false,"context_lines":[{"line_number":20,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":21,"context_line":"    \u0027IBPB\u0027,"},{"line_number":22,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":23,"context_line":"    \u0027AMD_SSBD\u0027,"},{"line_number":24,"context_line":"    \u0027AMD_NO_SSB\u0027,"},{"line_number":25,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":26,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":2,"id":"ffb9cba7_4877f0d5","line":24,"range":{"start_line":23,"start_character":0,"end_line":24,"end_character":17},"updated":"2019-04-24 15:43:21.000000000","message":"These will show up with _AMD_AMD_ in them (the first one comes from the module path).\n\n In [2]: ot.HW_CPU_AMD_AMD_NO_SSB\n Out[2]: \u0027HW_CPU_AMD_AMD_NO_SSB\u0027\n \n In [3]: ot.HW_CPU_AMD_AMD_SSBD\n Out[3]: \u0027HW_CPU_AMD_AMD_SSBD\u0027\n\nIs that intentional?","commit_id":"a26766a5c80411b478360797adef2d25e4f79ec2"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"39549c47863ec482a3dd04af5662620f1ea888b0","unresolved":false,"context_lines":[{"line_number":20,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":21,"context_line":"    \u0027IBPB\u0027,"},{"line_number":22,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":23,"context_line":"    \u0027AMD_SSBD\u0027,"},{"line_number":24,"context_line":"    \u0027AMD_NO_SSB\u0027,"},{"line_number":25,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":26,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":2,"id":"ffb9cba7_f14a4125","line":24,"range":{"start_line":23,"start_character":0,"end_line":24,"end_character":17},"in_reply_to":"ffb9cba7_4877f0d5","updated":"2019-04-25 09:08:11.000000000","message":"Hmm, that\u0027s not desirable.  I wonder if it can cause confusion, because:\n\n - For Intel, the CPU flag is: \u0027ssbd\u0027\n - And for AMD, the CPU flag is: \u0027amd-ssbd\u0027\n\nHowever, in our case, since we can deduce that these traits apply for AMD based on the module path, maybe I can rename them to:\n\n   - SSBD\n   - NO_SSB","commit_id":"a26766a5c80411b478360797adef2d25e4f79ec2"},{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"475f87c7ac102da62ba6e7e4063894bfe70857c2","unresolved":false,"context_lines":[{"line_number":20,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":21,"context_line":"    \u0027IBPB\u0027,"},{"line_number":22,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":23,"context_line":"    \u0027AMD_SSBD\u0027,"},{"line_number":24,"context_line":"    \u0027AMD_NO_SSB\u0027,"},{"line_number":25,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":26,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":2,"id":"ffb9cba7_5528e084","line":24,"range":{"start_line":23,"start_character":0,"end_line":24,"end_character":17},"in_reply_to":"ffb9cba7_4877f0d5","updated":"2019-04-24 21:49:55.000000000","message":"That seems wrong to me.","commit_id":"a26766a5c80411b478360797adef2d25e4f79ec2"},{"author":{"_account_id":1063,"name":"Ed Leafe","email":"ed@leafe.com","username":"ed-leafe"},"change_message_id":"d9d95160055f9ab19607bb74633f76c5a598dd83","unresolved":false,"context_lines":[{"line_number":20,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":21,"context_line":"    \u0027IBPB\u0027,"},{"line_number":22,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":23,"context_line":"    \u0027AMD_SSBD\u0027,"},{"line_number":24,"context_line":"    \u0027AMD_NO_SSB\u0027,"},{"line_number":25,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":26,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":2,"id":"ffb9cba7_111272b2","line":24,"range":{"start_line":23,"start_character":0,"end_line":24,"end_character":17},"in_reply_to":"ffb9cba7_f14a4125","updated":"2019-04-25 12:55:45.000000000","message":"Traits represent capabilities. A resource provider that doesn\u0027t have a specific capability isn\u0027t represented by having a NO_{trait_name} trait; it simply lacks that trait. This negative trait isn\u0027t needed.","commit_id":"a26766a5c80411b478360797adef2d25e4f79ec2"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"9b1677f62f79d7d8c92186907330bcebf548f37b","unresolved":false,"context_lines":[{"line_number":18,"context_line":"    \u0027SEV\u0027,"},{"line_number":19,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":20,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":21,"context_line":"    \u0027IBPB\u0027,"},{"line_number":22,"context_line":"    \u0027STIBP\u0027,"},{"line_number":23,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":24,"context_line":"    \u0027SSBD\u0027,"},{"line_number":25,"context_line":"    \u0027NO_SSB\u0027,"},{"line_number":26,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":27,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":4,"id":"dfbec78f_c7da7a76","line":25,"range":{"start_line":21,"start_character":3,"end_line":25,"end_character":13},"updated":"2019-05-15 08:01:34.000000000","message":"i dont think these traits should be added as they allow me to \nexpclitly target vulnerable systems.","commit_id":"0c43e3005986d340dcaad660180a6117f7e2a468"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"9b1677f62f79d7d8c92186907330bcebf548f37b","unresolved":false,"context_lines":[{"line_number":23,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":24,"context_line":"    \u0027SSBD\u0027,"},{"line_number":25,"context_line":"    \u0027NO_SSB\u0027,"},{"line_number":26,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":27,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":4,"id":"dfbec78f_87e00228","line":26,"range":{"start_line":26,"start_character":4,"end_line":26,"end_character":14},"updated":"2019-05-15 08:01:34.000000000","message":"this is the same on both intel and amd so we should just have one trait in the x86.py","commit_id":"0c43e3005986d340dcaad660180a6117f7e2a468"},{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"d6f0a629d65c595287ce2934864f7f3c5d3438d1","unresolved":false,"context_lines":[{"line_number":15,"context_line":""},{"line_number":16,"context_line":"TRAITS \u003d ["},{"line_number":17,"context_line":"    # ref: https://developer.amd.com/sev/"},{"line_number":18,"context_line":"    # NOTE(kchamart): This file is deprecated.  The \u0027SVM\u0027 trait is"},{"line_number":19,"context_line":"    # AMD-only, so it is copied to hw/cpu/amd.py; it is retained here"},{"line_number":20,"context_line":"    # not to cause Placement breakage.  All AMD-only traits are being"},{"line_number":21,"context_line":"    # trakced under: hw/cpu/amd.py.  And the traits common to both AMD"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_9a02a76e","line":18,"range":{"start_line":18,"start_character":53,"end_line":18,"end_character":56},"updated":"2019-05-28 18:22:14.000000000","message":"SEV","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"d6f0a629d65c595287ce2934864f7f3c5d3438d1","unresolved":false,"context_lines":[{"line_number":17,"context_line":"    # ref: https://developer.amd.com/sev/"},{"line_number":18,"context_line":"    # NOTE(kchamart): This file is deprecated.  The \u0027SVM\u0027 trait is"},{"line_number":19,"context_line":"    # AMD-only, so it is copied to hw/cpu/amd.py; it is retained here"},{"line_number":20,"context_line":"    # not to cause Placement breakage.  All AMD-only traits are being"},{"line_number":21,"context_line":"    # trakced under: hw/cpu/amd.py.  And the traits common to both AMD"},{"line_number":22,"context_line":"    # _and_ Intel are being tracked here: hw/cpu/x86/__init__.py."},{"line_number":23,"context_line":"    \u0027SEV\u0027,"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_5af8af79","line":20,"range":{"start_line":20,"start_character":6,"end_line":20,"end_character":37},"updated":"2019-05-28 18:22:14.000000000","message":"I suggest linking to https://docs.openstack.org/os-traits/latest/contributor/index.html#trait-lifecycle-policy and also mentioning that this trait was never used for anything, since the first bit of SEV code to use an SEV trait will land after this change - it\u0027s https://review.opendev.org/#/c/638680/ which has an explicit Depends-On against this change, and is actually blocked until this change merges *and* gets released.","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"d6f0a629d65c595287ce2934864f7f3c5d3438d1","unresolved":false,"context_lines":[{"line_number":18,"context_line":"    # NOTE(kchamart): This file is deprecated.  The \u0027SVM\u0027 trait is"},{"line_number":19,"context_line":"    # AMD-only, so it is copied to hw/cpu/amd.py; it is retained here"},{"line_number":20,"context_line":"    # not to cause Placement breakage.  All AMD-only traits are being"},{"line_number":21,"context_line":"    # trakced under: hw/cpu/amd.py.  And the traits common to both AMD"},{"line_number":22,"context_line":"    # _and_ Intel are being tracked here: hw/cpu/x86/__init__.py."},{"line_number":23,"context_line":"    \u0027SEV\u0027,"},{"line_number":24,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_1aeeb7b3","line":21,"range":{"start_line":21,"start_character":6,"end_line":21,"end_character":13},"updated":"2019-05-28 18:22:14.000000000","message":"tracked","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"698fdb6640ad50cc798941c12c1301fe0c3d1b40","unresolved":false,"context_lines":[{"line_number":18,"context_line":"    # NOTE(kchamart): This file is deprecated.  The \u0027SEV\u0027 trait is"},{"line_number":19,"context_line":"    # AMD-only, so it is copied to hw/cpu/amd.py; it is retained here"},{"line_number":20,"context_line":"    # not to cause Placement breakage.  All AMD-only traits are being"},{"line_number":21,"context_line":"    # tracked under: hw/cpu/amd.py.  And the traits common to both AMD"},{"line_number":22,"context_line":"    # _and_ Intel are being tracked here: hw/cpu/x86/__init__.py."},{"line_number":23,"context_line":"    #"},{"line_number":24,"context_line":"    # NOTE(aspiers): This trait was never used for anything, since the"}],"source_content_type":"text/x-python","patch_set":6,"id":"bfb3d3c7_36adbd9a","line":21,"range":{"start_line":21,"start_character":21,"end_line":21,"end_character":35},"updated":"2019-05-29 19:48:53.000000000","message":"hw/cpu/x86/amd.py","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"698fdb6640ad50cc798941c12c1301fe0c3d1b40","unresolved":false,"context_lines":[{"line_number":24,"context_line":"    # NOTE(aspiers): This trait was never used for anything, since the"},{"line_number":25,"context_line":"    # first bit of SEV code to use an SEV trait will land after this"},{"line_number":26,"context_line":"    # https://review.opendev.org/#/c/638680/ which has an explicit"},{"line_number":27,"context_line":"    # \u0027Depends-On\u0027 against the change I1c9a72d19ef (\"hw: cpu: Rework the"},{"line_number":28,"context_line":"    # directory layout; add missing traits\"), and is actually blocked"},{"line_number":29,"context_line":"    # until I1c9a72d19ef merges *and* gets released."},{"line_number":30,"context_line":"    \u0027SEV\u0027,"}],"source_content_type":"text/x-python","patch_set":6,"id":"bfb3d3c7_96f26999","line":27,"range":{"start_line":27,"start_character":38,"end_line":27,"end_character":50},"updated":"2019-05-29 19:48:53.000000000","message":"It\u0027s a little weird that this comment references its own change.","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"886997ff16fd3629abdadb8bf8b653fdc4fc7ca3","unresolved":false,"context_lines":[{"line_number":24,"context_line":"    # NOTE(aspiers): This trait was never used for anything, since the"},{"line_number":25,"context_line":"    # first bit of SEV code to use an SEV trait will land after this"},{"line_number":26,"context_line":"    # https://review.opendev.org/#/c/638680/ which has an explicit"},{"line_number":27,"context_line":"    # \u0027Depends-On\u0027 against the change I1c9a72d19ef (\"hw: cpu: Rework the"},{"line_number":28,"context_line":"    # directory layout; add missing traits\"), and is actually blocked"},{"line_number":29,"context_line":"    # until I1c9a72d19ef merges *and* gets released."},{"line_number":30,"context_line":"    \u0027SEV\u0027,"}],"source_content_type":"text/x-python","patch_set":6,"id":"bfb3d3c7_91583356","line":27,"range":{"start_line":27,"start_character":38,"end_line":27,"end_character":50},"in_reply_to":"bfb3d3c7_96f26999","updated":"2019-05-29 20:54:58.000000000","message":"Hehe, I felt so too.  That\u0027s why I wrote the note (by slightly editing Adam\u0027s original remark) to make sure I\u0027m pointing to the Change-Id and not the awkward \"this change\" (which would be weirder still when it gets merged).\n\nAs Adam noted, once it merges, the weirdness reduces. :-)","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"},{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"1a08ed51581dd727f0c92acf1b7448809f1151e8","unresolved":false,"context_lines":[{"line_number":24,"context_line":"    # NOTE(aspiers): This trait was never used for anything, since the"},{"line_number":25,"context_line":"    # first bit of SEV code to use an SEV trait will land after this"},{"line_number":26,"context_line":"    # https://review.opendev.org/#/c/638680/ which has an explicit"},{"line_number":27,"context_line":"    # \u0027Depends-On\u0027 against the change I1c9a72d19ef (\"hw: cpu: Rework the"},{"line_number":28,"context_line":"    # directory layout; add missing traits\"), and is actually blocked"},{"line_number":29,"context_line":"    # until I1c9a72d19ef merges *and* gets released."},{"line_number":30,"context_line":"    \u0027SEV\u0027,"}],"source_content_type":"text/x-python","patch_set":6,"id":"bfb3d3c7_d606a152","line":27,"range":{"start_line":27,"start_character":38,"end_line":27,"end_character":50},"in_reply_to":"bfb3d3c7_96f26999","updated":"2019-05-29 19:56:51.000000000","message":"It would be weird in the commit message, but if it merges then the comment is in the tree not just in the change, so it\u0027s not *too* weird :-)","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"}],"os_traits/hw/cpu/x86.py":[{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"8467ebae869e32b75ba1cd19736668ef53d69bbd","unresolved":false,"context_lines":[{"line_number":62,"context_line":"    \u0027VMX\u0027,"},{"line_number":63,"context_line":"    # ref: https://en.wikipedia.org/wiki/AMD-V"},{"line_number":64,"context_line":"    \u0027SVM\u0027,"},{"line_number":65,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005fintel_005fx86"},{"line_number":66,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":67,"context_line":"    \u0027PCID\u0027,"},{"line_number":68,"context_line":"    \u0027SPEC-CRTL\u0027,"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_5b4fd2bc","line":65,"range":{"start_line":65,"start_character":0,"end_line":65,"end_character":102},"updated":"2019-04-23 19:40:49.000000000","message":"Guess you\u0027ll want to noqa these comments?","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"653aee5a99e1fec96d7c1c6063eef37365469263","unresolved":false,"context_lines":[{"line_number":62,"context_line":"    \u0027VMX\u0027,"},{"line_number":63,"context_line":"    # ref: https://en.wikipedia.org/wiki/AMD-V"},{"line_number":64,"context_line":"    \u0027SVM\u0027,"},{"line_number":65,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005fintel_005fx86"},{"line_number":66,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":67,"context_line":"    \u0027PCID\u0027,"},{"line_number":68,"context_line":"    \u0027SPEC-CRTL\u0027,"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_db77373a","line":65,"range":{"start_line":65,"start_character":0,"end_line":65,"end_character":102},"in_reply_to":"ffb9cba7_5b4fd2bc","updated":"2019-04-24 07:58:59.000000000","message":"I think so.  Because Flake8 is complaining:\n\n[...]\n./os_traits/hw/cpu/x86.py:65:80: E501 line too long (102 \u003e 79 characters)\n    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005fintel_005fx86\n                                                                               ^\n./os_traits/hw/cpu/x86.py:71:80: E501 line too long (100 \u003e 79 characters)\n    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005famd_005fx86\n[...]","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"8467ebae869e32b75ba1cd19736668ef53d69bbd","unresolved":false,"context_lines":[{"line_number":65,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005fintel_005fx86"},{"line_number":66,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":67,"context_line":"    \u0027PCID\u0027,"},{"line_number":68,"context_line":"    \u0027SPEC-CRTL\u0027,"},{"line_number":69,"context_line":"    \u0027SSBD\u0027,"},{"line_number":70,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":71,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005famd_005fx86"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_5b76f208","line":68,"range":{"start_line":68,"start_character":10,"end_line":68,"end_character":14},"updated":"2019-04-23 19:40:49.000000000","message":"CTRL?","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"8467ebae869e32b75ba1cd19736668ef53d69bbd","unresolved":false,"context_lines":[{"line_number":65,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005fintel_005fx86"},{"line_number":66,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":67,"context_line":"    \u0027PCID\u0027,"},{"line_number":68,"context_line":"    \u0027SPEC-CRTL\u0027,"},{"line_number":69,"context_line":"    \u0027SSBD\u0027,"},{"line_number":70,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":71,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005famd_005fx86"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_bb692e26","line":68,"range":{"start_line":68,"start_character":9,"end_line":68,"end_character":10},"updated":"2019-04-23 19:40:49.000000000","message":"pretty sure we don\u0027t allow hyphens in trait names","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"653aee5a99e1fec96d7c1c6063eef37365469263","unresolved":false,"context_lines":[{"line_number":65,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005fintel_005fx86"},{"line_number":66,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":67,"context_line":"    \u0027PCID\u0027,"},{"line_number":68,"context_line":"    \u0027SPEC-CRTL\u0027,"},{"line_number":69,"context_line":"    \u0027SSBD\u0027,"},{"line_number":70,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":71,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005famd_005fx86"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_fb431bae","line":68,"range":{"start_line":68,"start_character":10,"end_line":68,"end_character":14},"in_reply_to":"ffb9cba7_5b76f208","updated":"2019-04-24 07:58:59.000000000","message":"Yes, will fix.","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"653aee5a99e1fec96d7c1c6063eef37365469263","unresolved":false,"context_lines":[{"line_number":65,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005fintel_005fx86"},{"line_number":66,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":67,"context_line":"    \u0027PCID\u0027,"},{"line_number":68,"context_line":"    \u0027SPEC-CRTL\u0027,"},{"line_number":69,"context_line":"    \u0027SSBD\u0027,"},{"line_number":70,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":71,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005famd_005fx86"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_bb8da332","line":68,"range":{"start_line":68,"start_character":9,"end_line":68,"end_character":10},"in_reply_to":"ffb9cba7_bb692e26","updated":"2019-04-24 07:58:59.000000000","message":"Yeah, realized. :-)","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"9b1677f62f79d7d8c92186907330bcebf548f37b","unresolved":false,"context_lines":[{"line_number":71,"context_line":"    # ref: https://qemu.weilnetz.de/doc/qemu-doc.html#important_005fcpu_005ffeatures_005famd_005fx86"},{"line_number":72,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":73,"context_line":"    \u0027IBPB\u0027,"},{"line_number":74,"context_line":"    \u0027VIRT-SSBD\u0027,"},{"line_number":75,"context_line":"    \u0027AMD-SSBD\u0027,"},{"line_number":76,"context_line":"    \u0027AMD-NO-SSB\u0027,"},{"line_number":77,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":78,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_aec56d90","line":75,"range":{"start_line":74,"start_character":4,"end_line":75,"end_character":15},"updated":"2019-05-15 08:01:34.000000000","message":"i would drop these and jsut use the \nSSBD trait above.","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"9b1677f62f79d7d8c92186907330bcebf548f37b","unresolved":false,"context_lines":[{"line_number":74,"context_line":"    \u0027VIRT-SSBD\u0027,"},{"line_number":75,"context_line":"    \u0027AMD-SSBD\u0027,"},{"line_number":76,"context_line":"    \u0027AMD-NO-SSB\u0027,"},{"line_number":77,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":78,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_cec22186","line":77,"range":{"start_line":77,"start_character":4,"end_line":77,"end_character":14},"updated":"2019-05-15 08:01:34.000000000","message":"delete\nthis is a dupe of line 70","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"8467ebae869e32b75ba1cd19736668ef53d69bbd","unresolved":false,"context_lines":[{"line_number":74,"context_line":"    \u0027VIRT-SSBD\u0027,"},{"line_number":75,"context_line":"    \u0027AMD-SSBD\u0027,"},{"line_number":76,"context_line":"    \u0027AMD-NO-SSB\u0027,"},{"line_number":77,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":78,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_9b554a53","line":77,"range":{"start_line":77,"start_character":5,"end_line":77,"end_character":12},"updated":"2019-04-23 19:40:49.000000000","message":"dup of L70?","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"377e3de1068804539473473fd983989dbf9b631e","unresolved":false,"context_lines":[{"line_number":74,"context_line":"    \u0027VIRT-SSBD\u0027,"},{"line_number":75,"context_line":"    \u0027AMD-SSBD\u0027,"},{"line_number":76,"context_line":"    \u0027AMD-NO-SSB\u0027,"},{"line_number":77,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":78,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_2613d65e","line":77,"range":{"start_line":77,"start_character":5,"end_line":77,"end_character":12},"in_reply_to":"ffb9cba7_5b84a70c","updated":"2019-04-24 08:12:53.000000000","message":"I think I should move these AMD flags I\u0027ve added to amd.py.\n\n(And move the existing \u0027SVM\u0027 in a separate patch.)","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"653aee5a99e1fec96d7c1c6063eef37365469263","unresolved":false,"context_lines":[{"line_number":74,"context_line":"    \u0027VIRT-SSBD\u0027,"},{"line_number":75,"context_line":"    \u0027AMD-SSBD\u0027,"},{"line_number":76,"context_line":"    \u0027AMD-NO-SSB\u0027,"},{"line_number":77,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":78,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":1,"id":"ffb9cba7_5b84a70c","line":77,"range":{"start_line":77,"start_character":5,"end_line":77,"end_character":12},"in_reply_to":"ffb9cba7_9b554a53","updated":"2019-04-24 07:58:59.000000000","message":"Whoops, yes; will fix.","commit_id":"627c50fb63403cc3e7f098263c5199c4103d584e"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"d19af29f4497c3f68333b83f9f2fd14303716a70","unresolved":false,"context_lines":[{"line_number":65,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":66,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":67,"context_line":"    \u0027PCID\u0027,"},{"line_number":68,"context_line":"    \u0027SPEC_CRTL\u0027,"},{"line_number":69,"context_line":"    \u0027SSBD\u0027,"},{"line_number":70,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":71,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":2,"id":"ffb9cba7_e39e05b7","line":68,"range":{"start_line":68,"start_character":10,"end_line":68,"end_character":14},"updated":"2019-04-24 15:43:21.000000000","message":"CTRL","commit_id":"a26766a5c80411b478360797adef2d25e4f79ec2"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"9b1677f62f79d7d8c92186907330bcebf548f37b","unresolved":false,"context_lines":[{"line_number":64,"context_line":"    \u0027SVM\u0027,"},{"line_number":65,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":66,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":67,"context_line":"    \u0027PCID\u0027,"},{"line_number":68,"context_line":"    \u0027SPEC_CRTL\u0027,"},{"line_number":69,"context_line":"    \u0027STIBP\u0027,"},{"line_number":70,"context_line":"    \u0027SSBD\u0027,"}],"source_content_type":"text/x-python","patch_set":4,"id":"dfbec78f_07ce52b3","line":67,"range":{"start_line":67,"start_character":3,"end_line":67,"end_character":11},"updated":"2019-05-15 08:01:34.000000000","message":"we should add this","commit_id":"0c43e3005986d340dcaad660180a6117f7e2a468"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"0da6f7f38ea414e87606fec0ca38c0c342ed934d","unresolved":false,"context_lines":[{"line_number":65,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":66,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":67,"context_line":"    \u0027PCID\u0027,"},{"line_number":68,"context_line":"    \u0027SPEC_CRTL\u0027,"},{"line_number":69,"context_line":"    \u0027STIBP\u0027,"},{"line_number":70,"context_line":"    \u0027SSBD\u0027,"},{"line_number":71,"context_line":"    \u0027PDPE1GB\u0027,"}],"source_content_type":"text/x-python","patch_set":4,"id":"dfbec78f_7396304f","line":68,"range":{"start_line":68,"start_character":10,"end_line":68,"end_character":14},"updated":"2019-05-10 19:29:41.000000000","message":"CTRL","commit_id":"0c43e3005986d340dcaad660180a6117f7e2a468"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"9b1677f62f79d7d8c92186907330bcebf548f37b","unresolved":false,"context_lines":[{"line_number":65,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":66,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":67,"context_line":"    \u0027PCID\u0027,"},{"line_number":68,"context_line":"    \u0027SPEC_CRTL\u0027,"},{"line_number":69,"context_line":"    \u0027STIBP\u0027,"},{"line_number":70,"context_line":"    \u0027SSBD\u0027,"},{"line_number":71,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":72,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":4,"id":"dfbec78f_47d8ca79","line":70,"range":{"start_line":68,"start_character":4,"end_line":70,"end_character":11},"updated":"2019-05-15 08:01:34.000000000","message":"as in the amd.py i dont think these shoudl be traits\n\nthat does not mean we should not support setting them via the nova.conf to the cpu model but they shoudl not be traits i can schedule on in my opinion as i can exploit these tratis to deploy a payload to a vulnerable host","commit_id":"0c43e3005986d340dcaad660180a6117f7e2a468"},{"author":{"_account_id":11604,"name":"sean mooney","email":"smooney@redhat.com","username":"sean-k-mooney"},"change_message_id":"9b1677f62f79d7d8c92186907330bcebf548f37b","unresolved":false,"context_lines":[{"line_number":68,"context_line":"    \u0027SPEC_CRTL\u0027,"},{"line_number":69,"context_line":"    \u0027STIBP\u0027,"},{"line_number":70,"context_line":"    \u0027SSBD\u0027,"},{"line_number":71,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":72,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":4,"id":"dfbec78f_67be2e00","line":71,"range":{"start_line":71,"start_character":2,"end_line":71,"end_character":14},"updated":"2019-05-15 08:01:34.000000000","message":"and we shoudl add this.\n\non x86 to be able to allocate 1G hugepages in a vm if the host dose not support this.\n\nas such if your vm will use 1G hugepages internally regardless of if the vm itself will be backed by hugepages you will need to scudle on this to ensure it lands on a host that support that feature in hardware.","commit_id":"0c43e3005986d340dcaad660180a6117f7e2a468"},{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"d6f0a629d65c595287ce2934864f7f3c5d3438d1","unresolved":false,"context_lines":[{"line_number":12,"context_line":"# License for the specific language governing permissions and limitations"},{"line_number":13,"context_line":"# under the License."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"# !NOTE(kchamart)! This file is deprecated (but is retained to not"},{"line_number":16,"context_line":"# break Placement) in favor of the \"New Layout\" below, where the common"},{"line_number":17,"context_line":"# traits for Intel and AMD are captured in x86/__init__.py.  And"},{"line_number":18,"context_line":"# the vendor-specific traits are captured in their corresponding files,"},{"line_number":19,"context_line":"# x86/amd.py and x86/intel.py."}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_da31ff5b","line":16,"range":{"start_line":15,"start_character":48,"end_line":16,"end_character":17},"updated":"2019-05-28 18:22:14.000000000","message":"Again maybe worth linking to https://docs.openstack.org/os-traits/latest/contributor/index.html#trait-lifecycle-policy ?","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"50b9c1007fa1f95e13ee755c3e32b1729cdceebe","unresolved":false,"context_lines":[{"line_number":12,"context_line":"# License for the specific language governing permissions and limitations"},{"line_number":13,"context_line":"# under the License."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"# !NOTE(kchamart)! This file is deprecated (but is retained to not"},{"line_number":16,"context_line":"# break Placement) in favor of the \"New Layout\" below, where the common"},{"line_number":17,"context_line":"# traits for Intel and AMD are captured in x86/__init__.py.  And"},{"line_number":18,"context_line":"# the vendor-specific traits are captured in their corresponding files,"},{"line_number":19,"context_line":"# x86/amd.py and x86/intel.py."}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_6d9cdc0d","line":16,"range":{"start_line":15,"start_character":48,"end_line":16,"end_character":17},"in_reply_to":"bfb3d3c7_3bd29d01","updated":"2019-05-28 23:11:35.000000000","message":"Yup, thanks for fixing up my fuzzy thinking - I knew that, but hadn\u0027t managed to clearly articulate it in my head until now.","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"2e63f93b8f1ed8d52aedaa2ef689ffdf7f7417e1","unresolved":false,"context_lines":[{"line_number":12,"context_line":"# License for the specific language governing permissions and limitations"},{"line_number":13,"context_line":"# under the License."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"# !NOTE(kchamart)! This file is deprecated (but is retained to not"},{"line_number":16,"context_line":"# break Placement) in favor of the \"New Layout\" below, where the common"},{"line_number":17,"context_line":"# traits for Intel and AMD are captured in x86/__init__.py.  And"},{"line_number":18,"context_line":"# the vendor-specific traits are captured in their corresponding files,"},{"line_number":19,"context_line":"# x86/amd.py and x86/intel.py."}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_3bd29d01","line":16,"range":{"start_line":15,"start_character":48,"end_line":16,"end_character":17},"in_reply_to":"bfb3d3c7_da31ff5b","updated":"2019-05-28 21:45:20.000000000","message":"You don\u0027t need to retain this file. You just need to make sure the contents are all included in x86/__init__.py.\n\nPlacement only \"breaks\" if we remove trait *strings* that used to be in the database.\n\nThe total list of string trait names is what\u0027s important.","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"}],"os_traits/hw/cpu/x86/__init__.py":[{"author":{"_account_id":11564,"name":"Chris Dent","email":"cdent@anticdent.org","username":"chdent"},"change_message_id":"676b875c6049ca905fab35476460326e58d4a5c1","unresolved":false,"context_lines":[{"line_number":62,"context_line":"    # NOTE(kchamart): The \u0027VMX\u0027 trait is Intel-only, and does not belong"},{"line_number":63,"context_line":"    # in this file (which is supposed to be a \"common\" file for all"},{"line_number":64,"context_line":"    # x86-related).  But we need to retain it here forever to not cause"},{"line_number":65,"context_line":"    # Placement breakage."},{"line_number":66,"context_line":"    \u0027VMX\u0027,"},{"line_number":67,"context_line":"    # ref: https://en.wikipedia.org/wiki/AMD-V"},{"line_number":68,"context_line":"    # NOTE(kchamart): The \u0027SVM\u0027 trait is AMD-only, and does not belong"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_ef776ed3","line":65,"updated":"2019-05-28 12:24:56.000000000","message":"Is the hope/expectation here that nothing has actually used HW_CPU_X86_VMX and this is here _solely_ to preserve/protect existing placement databases?\n\nBecause we definitely want to avoid the situation where people are now forced to annotate all their stuff with two traits which mean effectively the same thing.","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"2e63f93b8f1ed8d52aedaa2ef689ffdf7f7417e1","unresolved":false,"context_lines":[{"line_number":62,"context_line":"    # NOTE(kchamart): The \u0027VMX\u0027 trait is Intel-only, and does not belong"},{"line_number":63,"context_line":"    # in this file (which is supposed to be a \"common\" file for all"},{"line_number":64,"context_line":"    # x86-related).  But we need to retain it here forever to not cause"},{"line_number":65,"context_line":"    # Placement breakage."},{"line_number":66,"context_line":"    \u0027VMX\u0027,"},{"line_number":67,"context_line":"    # ref: https://en.wikipedia.org/wiki/AMD-V"},{"line_number":68,"context_line":"    # NOTE(kchamart): The \u0027SVM\u0027 trait is AMD-only, and does not belong"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_9badc99c","line":65,"in_reply_to":"bfb3d3c7_9524b8b0","updated":"2019-05-28 21:45:20.000000000","message":"Unfortunately, no, since libvirt was already exposing the trait under the old name, we do have to support both moving forward. I have a patch up [1] to make that work. I agree it\u0027s not ideal, but it\u0027s not hard to do, and this surely won\u0027t be the last time it comes up.\n\n(Whether we ultimately deprecate the old version of the trait and stop exposing it in a future release - that\u0027s another discussion I guess.)\n\n[1] https://review.opendev.org/660515","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"77bb62e9070d4c4fd59e8430c0c5dc85cf09b425","unresolved":false,"context_lines":[{"line_number":62,"context_line":"    # NOTE(kchamart): The \u0027VMX\u0027 trait is Intel-only, and does not belong"},{"line_number":63,"context_line":"    # in this file (which is supposed to be a \"common\" file for all"},{"line_number":64,"context_line":"    # x86-related).  But we need to retain it here forever to not cause"},{"line_number":65,"context_line":"    # Placement breakage."},{"line_number":66,"context_line":"    \u0027VMX\u0027,"},{"line_number":67,"context_line":"    # ref: https://en.wikipedia.org/wiki/AMD-V"},{"line_number":68,"context_line":"    # NOTE(kchamart): The \u0027SVM\u0027 trait is AMD-only, and does not belong"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_9524b8b0","line":65,"in_reply_to":"bfb3d3c7_ef776ed3","updated":"2019-05-28 18:39:41.000000000","message":"\u003e Is the hope/expectation here that nothing has actually used\n \u003e HW_CPU_X86_VMX and this is here _solely_ to preserve/protect\n \u003e existing placement databases?\n\nYes, I think so.  I\u0027ll wait for Eric to double-confirm, as I don\u0027t feel qualified to talk authoritatively on the intersection of \u0027os_traits\u0027 and Placement, afraid.\n\n \u003e \n \u003e Because we definitely want to avoid the situation where people are\n \u003e now forced to annotate all their stuff with two traits which mean\n \u003e effectively the same thing.\n\nUnderstood.","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"2e63f93b8f1ed8d52aedaa2ef689ffdf7f7417e1","unresolved":false,"context_lines":[{"line_number":74,"context_line":"    # included by default in any of the Intel and AMD CPU models.  So"},{"line_number":75,"context_line":"    # this should be explicitly turned on for all Intel and AMD CPU"},{"line_number":76,"context_line":"    # models."},{"line_number":77,"context_line":"    \u0027PDPE1GB\u0027,"},{"line_number":78,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":79,"context_line":"    # Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in"},{"line_number":80,"context_line":"    # some operating systems.  This flag must be explicitly turned on"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_9bbaa96b","line":77,"range":{"start_line":77,"start_character":5,"end_line":77,"end_character":12},"updated":"2019-05-28 21:45:20.000000000","message":"✔","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"2e63f93b8f1ed8d52aedaa2ef689ffdf7f7417e1","unresolved":false,"context_lines":[{"line_number":81,"context_line":"    # for *all* Intel and AMD CPU models.  (Prerequisite: host CPU"},{"line_number":82,"context_line":"    # microcode needs to support this feature before it can be used for"},{"line_number":83,"context_line":"    # guest CPUs)."},{"line_number":84,"context_line":"    \u0027STIBP\u0027,"},{"line_number":85,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_3bb37d9a","line":84,"range":{"start_line":84,"start_character":5,"end_line":84,"end_character":10},"updated":"2019-05-28 21:45:20.000000000","message":"✔","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"}],"os_traits/hw/cpu/x86/amd.py":[{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"d6f0a629d65c595287ce2934864f7f3c5d3438d1","unresolved":false,"context_lines":[{"line_number":14,"context_line":""},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"TRAITS \u003d ["},{"line_number":17,"context_line":"    # ref: https://developer.amd.com/sev/"},{"line_number":18,"context_line":"    \u0027SEV\u0027,"},{"line_number":19,"context_line":"    # ref: https://en.wikipedia.org/wiki/AMD-V"},{"line_number":20,"context_line":"    \u0027SVM\u0027,"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_3adcdbe2","line":17,"updated":"2019-05-28 18:22:14.000000000","message":"I know this URL probably came from me originally, but with hindsight, http://specs.openstack.org/openstack/nova-specs/specs/train/approved/amd-sev-libvirt-support.html is more helpful.","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"2e63f93b8f1ed8d52aedaa2ef689ffdf7f7417e1","unresolved":false,"context_lines":[{"line_number":23,"context_line":"    \u0027IBPB\u0027,"},{"line_number":24,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":25,"context_line":"    \u0027SSBD\u0027,"},{"line_number":26,"context_line":"    \u0027NO_SSB\u0027,"},{"line_number":27,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_9b6f09fb","line":26,"updated":"2019-05-28 21:45:20.000000000","message":"✔\n\nAny reason not to alphabetize these four?","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"50b9c1007fa1f95e13ee755c3e32b1729cdceebe","unresolved":false,"context_lines":[{"line_number":23,"context_line":"    \u0027IBPB\u0027,"},{"line_number":24,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":25,"context_line":"    \u0027SSBD\u0027,"},{"line_number":26,"context_line":"    \u0027NO_SSB\u0027,"},{"line_number":27,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_f0197f79","line":26,"in_reply_to":"bfb3d3c7_9b6f09fb","updated":"2019-05-28 23:11:35.000000000","message":"If we want to be really OCD, perhaps it\u0027s worth writing a linter to check that everything is alphabetically sorted.  Normally I\u0027d say that\u0027s overkill, but I\u0027ve seen it done elsewhere within OpenStack, so ...","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"574b71d83801ab6ba708096039a21f1a6e6b09b1","unresolved":false,"context_lines":[{"line_number":23,"context_line":"    \u0027IBPB\u0027,"},{"line_number":24,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":25,"context_line":"    \u0027SSBD\u0027,"},{"line_number":26,"context_line":"    \u0027NO_SSB\u0027,"},{"line_number":27,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_c33910d7","line":26,"in_reply_to":"bfb3d3c7_f0197f79","updated":"2019-05-29 10:26:32.000000000","message":"I\u0027m not suggesting sorting the whole file. I would still like to keep e.g. these security traits (for all of whom the same comment applies) together in a chunk.","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"698fdb6640ad50cc798941c12c1301fe0c3d1b40","unresolved":false,"context_lines":[{"line_number":13,"context_line":"# under the License."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"TRAITS \u003d ["},{"line_number":17,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":18,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":19,"context_line":"    \u0027IBPB\u0027,"}],"source_content_type":"text/x-python","patch_set":6,"id":"bfb3d3c7_76bed5b4","line":16,"updated":"2019-05-29 19:48:53.000000000","message":"In case you respin:\n\nTo recap the conversation at [1] I actually prefer not sorting the *whole* file, as I think it still makes sense to group e.g. all the traits that relate to [2] together. I was saying sorting within that group would be nice.\n\n[1] https://review.opendev.org/#/c/655193/5/os_traits/hw/cpu/x86/amd.py@26\n[2] https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"886997ff16fd3629abdadb8bf8b653fdc4fc7ca3","unresolved":false,"context_lines":[{"line_number":13,"context_line":"# under the License."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"TRAITS \u003d ["},{"line_number":17,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":18,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":19,"context_line":"    \u0027IBPB\u0027,"}],"source_content_type":"text/x-python","patch_set":6,"id":"bfb3d3c7_0c218c9f","line":16,"in_reply_to":"bfb3d3c7_76bed5b4","updated":"2019-05-29 20:54:58.000000000","message":"\u003e In case you respin:\n \u003e \n \u003e To recap the conversation at [1] I actually prefer not sorting the\n \u003e *whole* file, as I think it still makes sense to group e.g. all the\n \u003e traits that relate to [2] together. I was saying sorting within\n \u003e that group would be nice.\n\nIndeed, reckless me, you actually said much in [1], \"Any reason not to alphabetize these four\".  And I gratuitously sorted the *entire* file.  Will respin, and only sort just the four you noted.\n\n \u003e \n \u003e [1] https://review.opendev.org/#/c/655193/5/os_traits/hw/cpu/x86/amd.py@26\n \u003e [2] https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"},{"author":{"_account_id":2394,"name":"Adam Spiers","email":"aspiers@suse.com","username":"adam.spiers"},"change_message_id":"1a08ed51581dd727f0c92acf1b7448809f1151e8","unresolved":false,"context_lines":[{"line_number":13,"context_line":"# under the License."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"TRAITS \u003d ["},{"line_number":17,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":18,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":19,"context_line":"    \u0027IBPB\u0027,"}],"source_content_type":"text/x-python","patch_set":6,"id":"bfb3d3c7_b6f76d59","line":16,"in_reply_to":"bfb3d3c7_76bed5b4","updated":"2019-05-29 19:56:51.000000000","message":"Hah yeah, that was the one remaining nit which I almost mentioned, but I rounded up +0.99 to +1 :-)","commit_id":"a6b1a5e308b782fc58783d80892d936948d92b3b"}],"os_traits/hw/cpu/x86/intel.py":[{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"2e63f93b8f1ed8d52aedaa2ef689ffdf7f7417e1","unresolved":false,"context_lines":[{"line_number":18,"context_line":"    \u0027VMX\u0027,"},{"line_number":19,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":20,"context_line":"    # (Important CPU features for Intel x86 hosts)"},{"line_number":21,"context_line":"    \u0027PCID\u0027,"},{"line_number":22,"context_line":"    \u0027SSBD\u0027,"},{"line_number":23,"context_line":"    \u0027SPEC_CTRL\u0027,"},{"line_number":24,"context_line":"    \u0027MD_CLEAR\u0027,"},{"line_number":25,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":5,"id":"bfb3d3c7_3b785dc2","line":24,"range":{"start_line":21,"start_character":0,"end_line":24,"end_character":15},"updated":"2019-05-28 21:45:20.000000000","message":"all present and accounted for.\n\nAny reason not to alphabetize these?","commit_id":"b60ee5e5eae299f68c0997820015beca2ceacd8b"}]}