)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[{"line_number":32,"context_line":"needed.)"},{"line_number":33,"context_line":""},{"line_number":34,"context_line":"(*) Introduce a new cpu/x86 directory; and vendor-specific files: amd.py"},{"line_number":35,"context_line":"    and intel.py; with __init__.py containing the *common* stuff ("},{"line_number":36,"context_line":""},{"line_number":37,"context_line":"    - hw/cpu/x86/amd.py  (AMD-specific)"},{"line_number":38,"context_line":"    - hw/cpu/x86/intel.py  (Intel-specific)"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"bfb3d3c7_bf3b5dcf","line":35,"range":{"start_line":35,"start_character":65,"end_line":35,"end_character":66},"updated":"2019-05-20 21:23:28.000000000","message":"x","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[{"line_number":40,"context_line":""},{"line_number":41,"context_line":"       ---"},{"line_number":42,"context_line":""},{"line_number":43,"context_line":"    - hw/cpy/x86.py  (Contents of this file are moved into"},{"line_number":44,"context_line":"      x86/__init__.py.)"},{"line_number":45,"context_line":"    - hw/cpu/amd.py  (Deprecate it with a comment.)"},{"line_number":46,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"bfb3d3c7_9f3219f1","line":43,"range":{"start_line":43,"start_character":9,"end_line":43,"end_character":12},"updated":"2019-05-20 21:23:28.000000000","message":"cpu","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[{"line_number":42,"context_line":""},{"line_number":43,"context_line":"    - hw/cpy/x86.py  (Contents of this file are moved into"},{"line_number":44,"context_line":"      x86/__init__.py.)"},{"line_number":45,"context_line":"    - hw/cpu/amd.py  (Deprecate it with a comment.)"},{"line_number":46,"context_line":""},{"line_number":47,"context_line":"(*) Add various missing CPU flags to x86/intel.py and x86/amd.py"},{"line_number":48,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"bfb3d3c7_7f1ba51a","line":45,"range":{"start_line":45,"start_character":6,"end_line":45,"end_character":51},"updated":"2019-05-20 21:23:28.000000000","message":"don\u0027t see this in this patch","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"3e8f8f6de78d8120539ec7838393f6e032877f0c","unresolved":false,"context_lines":[{"line_number":42,"context_line":""},{"line_number":43,"context_line":"    - hw/cpy/x86.py  (Contents of this file are moved into"},{"line_number":44,"context_line":"      x86/__init__.py.)"},{"line_number":45,"context_line":"    - hw/cpu/amd.py  (Deprecate it with a comment.)"},{"line_number":46,"context_line":""},{"line_number":47,"context_line":"(*) Add various missing CPU flags to x86/intel.py and x86/amd.py"},{"line_number":48,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"bfb3d3c7_13605da5","line":45,"range":{"start_line":45,"start_character":6,"end_line":45,"end_character":51},"in_reply_to":"bfb3d3c7_7f1ba51a","updated":"2019-05-21 08:47:39.000000000","message":"Missed to commit it; will fix.","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[{"line_number":46,"context_line":""},{"line_number":47,"context_line":"(*) Add various missing CPU flags to x86/intel.py and x86/amd.py"},{"line_number":48,"context_line":""},{"line_number":49,"context_line":"(*) Move, from x86.py, flags like \"VMX\" (Intel) and \"SVM\" (AMD) into"},{"line_number":50,"context_line":"    corresponding vendor-specific files."},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"References:"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"bfb3d3c7_bf403d37","line":49,"range":{"start_line":49,"start_character":4,"end_line":49,"end_character":8},"updated":"2019-05-20 21:23:28.000000000","message":"alas, copy, and deprecate the old ones with a comment.\n\n[Later] ...which you did in the actual code, so ++. But could reword this in the commit message so future me doesn\u0027t freak out.","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"3e8f8f6de78d8120539ec7838393f6e032877f0c","unresolved":false,"context_lines":[{"line_number":46,"context_line":""},{"line_number":47,"context_line":"(*) Add various missing CPU flags to x86/intel.py and x86/amd.py"},{"line_number":48,"context_line":""},{"line_number":49,"context_line":"(*) Move, from x86.py, flags like \"VMX\" (Intel) and \"SVM\" (AMD) into"},{"line_number":50,"context_line":"    corresponding vendor-specific files."},{"line_number":51,"context_line":""},{"line_number":52,"context_line":"References:"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"bfb3d3c7_b347111e","line":49,"range":{"start_line":49,"start_character":4,"end_line":49,"end_character":8},"in_reply_to":"bfb3d3c7_bf403d37","updated":"2019-05-21 08:47:39.000000000","message":"Yeah, sorry.  Will reword.","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"}],"os_traits/hw/cpu/x86/__init__.py":[{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[{"line_number":58,"context_line":"    \u0027TSX\u0027,"},{"line_number":59,"context_line":"    # ref: https://en.wikipedia.org/wiki/Advanced_Synchronization_Facility"},{"line_number":60,"context_line":"    \u0027ASF\u0027,"},{"line_number":61,"context_line":"    # ref: https://en.wikipedia.org/wiki/VT-x"},{"line_number":62,"context_line":"    # NOTE(kchamart) This Intel \u0027VMX\u0027 trait is Intel-specific, and does"},{"line_number":63,"context_line":"    # does not belong in this file (which is supposed to be a \"common\""},{"line_number":64,"context_line":"    # file for all x86-related).  But we need to retain it here forever"}],"source_content_type":"text/x-python","patch_set":3,"id":"bfb3d3c7_7fbf25fb","line":61,"updated":"2019-05-20 21:23:28.000000000","message":"Ugh, we\u0027re going to have to figure out how to make this work in nova. The only way to do it will be to expose *both* versions of these traits. I wonder if it\u0027s worth it...","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"fa6528d036e4755b14068dfd00db91e0ca21559b","unresolved":false,"context_lines":[{"line_number":58,"context_line":"    \u0027TSX\u0027,"},{"line_number":59,"context_line":"    # ref: https://en.wikipedia.org/wiki/Advanced_Synchronization_Facility"},{"line_number":60,"context_line":"    \u0027ASF\u0027,"},{"line_number":61,"context_line":"    # ref: https://en.wikipedia.org/wiki/VT-x"},{"line_number":62,"context_line":"    # NOTE(kchamart) This Intel \u0027VMX\u0027 trait is Intel-specific, and does"},{"line_number":63,"context_line":"    # does not belong in this file (which is supposed to be a \"common\""},{"line_number":64,"context_line":"    # file for all x86-related).  But we need to retain it here forever"}],"source_content_type":"text/x-python","patch_set":3,"id":"bfb3d3c7_fafd4e3a","line":61,"in_reply_to":"bfb3d3c7_73a99979","updated":"2019-05-21 20:37:22.000000000","message":"\u003e I\u0027m not sure on how to make it work.\n\nSomething like this: https://review.opendev.org/660515\n\n \u003e And yes: I also wonder *is*\n \u003e it worth it?  (Probably in the long-term, it is?)\n\nDunno. It\u0027s pretty inexpensive to do it, and it seems like it\u0027s inevitable that we\u0027ll need a solution like this eventually. So...","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"3e8f8f6de78d8120539ec7838393f6e032877f0c","unresolved":false,"context_lines":[{"line_number":58,"context_line":"    \u0027TSX\u0027,"},{"line_number":59,"context_line":"    # ref: https://en.wikipedia.org/wiki/Advanced_Synchronization_Facility"},{"line_number":60,"context_line":"    \u0027ASF\u0027,"},{"line_number":61,"context_line":"    # ref: https://en.wikipedia.org/wiki/VT-x"},{"line_number":62,"context_line":"    # NOTE(kchamart) This Intel \u0027VMX\u0027 trait is Intel-specific, and does"},{"line_number":63,"context_line":"    # does not belong in this file (which is supposed to be a \"common\""},{"line_number":64,"context_line":"    # file for all x86-related).  But we need to retain it here forever"}],"source_content_type":"text/x-python","patch_set":3,"id":"bfb3d3c7_73a99979","line":61,"in_reply_to":"bfb3d3c7_7fbf25fb","updated":"2019-05-21 08:47:39.000000000","message":"I\u0027m not sure on how to make it work.  And yes: I also wonder *is* it worth it?  (Probably in the long-term, it is?)","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[{"line_number":69,"context_line":"    # belong in this \"common\" file.  But we need to retain it here"},{"line_number":70,"context_line":"    # forever to not cause Placement breakage."},{"line_number":71,"context_line":"    \u0027SVM\u0027,"},{"line_number":72,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":3,"id":"bfb3d3c7_9f6a197e","line":72,"updated":"2019-05-20 21:23:28.000000000","message":"should stibp and pdpe1gb be here?","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"3e8f8f6de78d8120539ec7838393f6e032877f0c","unresolved":false,"context_lines":[{"line_number":69,"context_line":"    # belong in this \"common\" file.  But we need to retain it here"},{"line_number":70,"context_line":"    # forever to not cause Placement breakage."},{"line_number":71,"context_line":"    \u0027SVM\u0027,"},{"line_number":72,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":3,"id":"bfb3d3c7_d3b165e3","line":72,"in_reply_to":"bfb3d3c7_9f6a197e","updated":"2019-05-21 08:47:39.000000000","message":"Yes.  Will add.","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"}],"os_traits/hw/cpu/x86/amd.py":[{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[{"line_number":21,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":22,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":23,"context_line":"    \u0027IBPB\u0027,"},{"line_number":24,"context_line":"    \u0027STIBP\u0027,"},{"line_number":25,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":26,"context_line":"    \u0027SSBD\u0027,"},{"line_number":27,"context_line":"    \u0027NO_SSB\u0027,"}],"source_content_type":"text/x-python","patch_set":3,"id":"bfb3d3c7_1f5f09e3","line":24,"range":{"start_line":24,"start_character":5,"end_line":24,"end_character":10},"updated":"2019-05-20 21:23:28.000000000","message":"This is also listed under Intel. Are the two different enough that they need to be differentiated at the trait level?","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"3e8f8f6de78d8120539ec7838393f6e032877f0c","unresolved":false,"context_lines":[{"line_number":21,"context_line":"    # ref: https://git.qemu.org/?p\u003dqemu.git;a\u003dblob;f\u003ddocs/qemu-cpu-models.texi"},{"line_number":22,"context_line":"    # (Important CPU features for AMD x86 hosts)"},{"line_number":23,"context_line":"    \u0027IBPB\u0027,"},{"line_number":24,"context_line":"    \u0027STIBP\u0027,"},{"line_number":25,"context_line":"    \u0027VIRT_SSBD\u0027,"},{"line_number":26,"context_line":"    \u0027SSBD\u0027,"},{"line_number":27,"context_line":"    \u0027NO_SSB\u0027,"}],"source_content_type":"text/x-python","patch_set":3,"id":"bfb3d3c7_13d37d3a","line":24,"range":{"start_line":24,"start_character":5,"end_line":24,"end_character":10},"in_reply_to":"bfb3d3c7_1f5f09e3","updated":"2019-05-21 08:47:39.000000000","message":"No, it doesn\u0027t; it\u0027s my recklessness.\n\nWill remove it from here; it belongs to the common __init__.py.","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"bfb3d3c7_3f052dc3","line":29,"updated":"2019-05-20 21:23:28.000000000","message":"missing pdpe1gb (also common to Intel)","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"3e8f8f6de78d8120539ec7838393f6e032877f0c","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"bfb3d3c7_9373ed80","line":29,"in_reply_to":"bfb3d3c7_3f052dc3","updated":"2019-05-21 08:47:39.000000000","message":"Will add \u0027pdpe1gb\u0027 to the common __init__.py file","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"}],"os_traits/hw/cpu/x86/intel.py":[{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[{"line_number":21,"context_line":"    \u0027PCID\u0027,"},{"line_number":22,"context_line":"    \u0027SSBD\u0027,"},{"line_number":23,"context_line":"    \u0027SPEC_CTRL\u0027,"},{"line_number":24,"context_line":"    \u0027STIBP\u0027,"},{"line_number":25,"context_line":"    \u0027MD_CLEAR\u0027,"},{"line_number":26,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":3,"id":"bfb3d3c7_ff0eb5e3","line":24,"range":{"start_line":24,"start_character":5,"end_line":24,"end_character":10},"updated":"2019-05-20 21:23:28.000000000","message":"common to AMD, see note there","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[{"line_number":22,"context_line":"    \u0027SSBD\u0027,"},{"line_number":23,"context_line":"    \u0027SPEC_CTRL\u0027,"},{"line_number":24,"context_line":"    \u0027STIBP\u0027,"},{"line_number":25,"context_line":"    \u0027MD_CLEAR\u0027,"},{"line_number":26,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":3,"id":"bfb3d3c7_ff279563","line":25,"range":{"start_line":25,"start_character":5,"end_line":25,"end_character":13},"updated":"2019-05-20 21:23:28.000000000","message":"Where did this come from? I don\u0027t see it in the reference.","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":6962,"name":"Kashyap Chamarthy","email":"kchamart@redhat.com","username":"kashyapc"},"change_message_id":"3e8f8f6de78d8120539ec7838393f6e032877f0c","unresolved":false,"context_lines":[{"line_number":22,"context_line":"    \u0027SSBD\u0027,"},{"line_number":23,"context_line":"    \u0027SPEC_CTRL\u0027,"},{"line_number":24,"context_line":"    \u0027STIBP\u0027,"},{"line_number":25,"context_line":"    \u0027MD_CLEAR\u0027,"},{"line_number":26,"context_line":"]"}],"source_content_type":"text/x-python","patch_set":3,"id":"bfb3d3c7_539ed563","line":25,"range":{"start_line":25,"start_character":5,"end_line":25,"end_character":13},"in_reply_to":"bfb3d3c7_ff279563","updated":"2019-05-21 08:47:39.000000000","message":"This is brand new (from a week-ish ago); it is mitigation for the \"MDS\" attacks (or \"ZombieLoad\" and friends).  It is being added to QEMU and libvirt upstream[1][2].  And the reference will be updated.  \n\nFrom the QEMU patch[1]:\n\n\"This patch series provides the new \"md-clear\" feature that is used for mitigation with CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091.\"\n\n[1] https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg03473.html (\"x86/cpu: add \"md-clear\" feature for MDS security flaws\")\n[2] https://www.redhat.com/archives/libvir-list/2019-May/msg00384.html (\"cpu_map: Define md-clear CPUID bit\")","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"},{"author":{"_account_id":14070,"name":"Eric Fried","email":"openstack@fried.cc","username":"efried"},"change_message_id":"41c66f0ed5f1df7e4f54de924a6a77b1f060d6e4","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"bfb3d3c7_bff83dc4","line":27,"updated":"2019-05-20 21:23:28.000000000","message":"missing pdpe1gb, see other comments","commit_id":"9e185aefc08e191d74376d5ffebf737a57afb5e3"}]}